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8790b?dflash?10/2013 features ? single 2.3v - 3.6v or 2.5v - 3.6v supply ? serial peripheral interface (spi) compatible ? supports spi modes 0 and 3 ? supports rapids ? operation ? supports dual-input and quad-input buffer write ? supports dual-output and quad-output read ? very high operating frequencies ? 85mhz (for spi) ? 85mhz (for dual-i/o and quad-i/o) ? clock-to-output time (t v ) of 6ns maximum ? user configurable page size ? 512 bytes per page ? 528 bytes per page (default) ? page size can be factory pre-configured for 512 bytes ? two fully independent sram data buffers (512/528 bytes) ? allows receiving data while reprogramming the main memory array ? flexible programming options ? byte/page program (1 to 512/528 bytes) directly into main memory ? buffer write ? buffer to main me mory page program ? flexible erase options ? page erase (512/528 bytes), block erase (4kb) ? sector erase (128kb), chip erase (16-mbits) ? program and erase suspend/resume ? advanced hardware and software data protection features ? individual sector protection ? individual sector lockdown to make any sector permanently read-only ? 128-byte, one-time programmable (otp) security register ? 64 bytes factory programmed with a unique identifier ? 64 bytes user programmable ? hardware and software controlled reset options ? jedec standard manufacturer and device id read ? low-power dissipation ? 500na ultra-deep power-down current (typical) ? 3a deep power-down current (typical) ? 25a standby current (typical) ? 11ma active read current (typical at 20mhz) ? endurance: 100,000 program/erase cycle s per page minimum (50,000 cycles for extended temperature option) ? data retention: 20 years ? complies with full industrial temperature range (extended temperature optional) ? green (pb/halide-free/rohs compliant) packaging options ? 8-lead soic (0.150" wide and 0.208" wide) ? 8-pad ultra-thin dfn (5 x 6 x 0.6mm) ? 9-ball ultra-thin ubga (6 x 6 x 0.6mm) at45dq161 16-mbit dataflash (with extra 512-kbits), 2.3v or 2.5v minimum spi serial flash memory with dual-i/o and quad-i/o support preliminary datasheet
2 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 description the at45dq161 is a 2.3v or 2.5v minimum, serial-inter face sequential access flash memory ideally suited for a wide variety of digital voice, image, program code, and data storage applications. the at45dq161 also supports dual-i/o, quad-i/o and the rapids serial interface for applications requiring very high speed operation. its 17,301,504 bits of memory are organized as 4,096 pages of 512 bytes or 528 bytes each. in addition to the main memory, the at45dq161 also contains two sram buffers of 512/528 bytes each. the buffers allow receiving of data while a page in the main memory is being reprogrammed. interleaving between both buffers can dramatically increase a system's ability to write a continuous data stream. in addition, the sram buffers can be used as additional system scratch pad memory, and e 2 prom emulation (bit or byte alterability) can be easily handled with a self-contained three step read-modify-write operation. unlike conventional flash memories that are accessed randomly with multiple address lines and a parallel interface, the dataflash ? uses a serial interface to sequentially access its data. the simple sequential access dramatically reduces active pin count, facilitates simplified hardware layout, increases system reliability, minimizes switching noise, and reduces package size. the device is optimized for use in many commercial and industrial applications where high- density, low-pin count, low-voltage, and low-power are essential. to allow for simple in-system re-programmability, the at 45dq161 does not require high input voltages for programming. the device operates from a single 2.3v to 3.6v or 2.5v to 3.6v power supply for the erase and program and read operations. the at45dq161 is enabled through the chip select pin (cs ) and accessed via a 3-wire interface consisting of the serial input (si), serial output (so), and the serial clock (sck). all programming and erase cycles are self-timed. 1. pin configurations and pinouts figure 1-1. pinouts note: 1. the metal pad on the bottom of the udfn package is not internally connected to a voltage potential. this pad can be a ?no connect? or connected to gnd. 1 2 3 4 8 7 6 5 si (i/o 0 ) sck reset (i/o 3 ) cs so (i/o 1 ) gnd v cc wp (i/o 2 ) 8-lead soic top view si (i/o 0 ) sck reset (i/o 3 ) cs so (i/o 1 ) gnd v cc wp (i/o 2 ) 8 7 6 5 1 2 3 4 8-pad udfn top view sck gnd v cc wp nc cs so si rst 9-ball ubga top view
3 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 table 1-1. pin configurations symbol name and function asserted state type cs chip select: asserting the cs pin selects the device. when the cs pin is deasserted, the device will be deselected and normally be placed in the standby mode (not deep power-down mode) and the output pin (so) will be in a high-impedance state. when the device is deselected, data will not be accepted on the input pin (si). a high-to-low transition on the cs pin is required to start an operation and a low-to-high transition is required to end an operation. when end ing an internally self-timed operation such as a program or erase cycle, t he device will not enter the standby mode until the completion of the operation. low input sck serial clock: this pin is used to provide a clock to the device and is used to control the flow of data to and from the device. command, address, and input data present on the si pin is always latched on the rising edge of sck, wh ile output data on the so pin is always clocked out on the falling edge of sck. ? input si (i/o 0 ) serial input (i/o 0 ): the si pin is used to shift data into the device. the si pin is used for all data input including command and address sequences . data on the si pin is always latched on the rising edge of sck. with the dual-output and quad-o utput read array commands, th e si pin becomes an output pin (i/o 0 ) and, along with other pins, allows two bits (on i/o 1-0 ) or four bits (on i/o 3-0 ) of data to be clocked out on every falling edge of sck. to maintain consistency with spi nomenclature, the si (i/o 0 ) pin will be referenced as si throughout the document with exception to sections dealing with the dual-output and quad-output read array commands in which it will be referenced as i/o 0 . data present on the si pin will be ignored whenever the device is deselected (cs is deasserted). ? input/ output so (i/o 1 ) serial output (i/o 1 ): the so pin is used to shift data out from the device. data on the so pin is always clocked out on the falling edge of sck. with the dual-output and quad-output read arra y commands, the so pin is used as an output pin (i/o 1 ) in conjunction with other pins to allow two bits (on i/o 1-0 ) or four bits (on i/o 3-0 ) of data to be clocked out on every falling edge of sck. to maintain consistency with spi nomenclature, the so (i/o 1 ) pin will be referenced as so throughout the document with exception to sections dealing with the dual-out put and quad-output read array commands in which it will be referenced as i/o 1 . the so pin will be in a high-impedance state whenever the device is deselected (cs is deasserted). ? input/ output
4 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 wp (i/o 2 ) write protect (i/o 2 ): when the wp pin is asserted, all sectors s pecified for protection by the sector protection register will be protected a gainst program and erase operations regardless of whether the enable sector protection command has been issued or not. the wp pin functions independently of the software controlled protection method. after the wp pin goes low, the contents of the sector pr otection register cannot be modified. the wp pin must be driven at all times or pulled-high using an external pull-up resistor. if a program or erase command is issued to the device while the wp pin is asserted, the device will simply ignore the command and perform no operation. the device will return to the idle state once the cs pin has been deasserted. the enabl e sector protection command and the sector lockdown command, however, will be recognized by the device when the wp pin is asserted. the wp pin is internally pulled-high and may be le ft floating if hardware controlled protection will not be used. however, it is recommended that the wp pin also be externally connected to v cc whenever possible. with the quad-output read array command, the wp pin becomes an output pin (i/o 2 ) and, when used with other pins, allows four bits (on i/o 3-0 ) of data to be clocked out on every falling edge of sck. the qe bit in the configurat ion register must be set in order for the wp pin to be used as an i/o data pin. low input/ output reset (i/o 3 ) reset (i/o 3 ): a low state on the reset pin (reset ) will terminate the operation in progress and reset the internal state machine to an idle stat e. the device will remain in the reset condition as long as a low level is present on the reset pin. normal operation can resume once the reset pin is brought back to a high level. with the quad-out put read array co mmand, the reset pin becomes an output pin (i/o 3 ) and, when used with other pins, allows four bits (on i/o 3-0 ) of data to be clocked out on every falling edge of sck. the qe bit in the configuration register must be set in order for the reset pin to be used as an i/o data pin. the device incorporates an internal power-on rese t circuit, so there are no restrictions on the reset pin during power-on sequences. if this pin and feature is not utilized, then it is recommended that the reset pin be driven high externally. low input/ output v cc device power supply: the v cc pin is used to supply the source voltage to the device. operations at invalid v cc voltages may produce spurious results and should not be attempted. ? power gnd ground: the ground reference for the power supply. gnd should be conn ected to the system ground. ? ground table 1-1. pin configurations (continued) symbol name and function asserted state type
5 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 2. block diagram figure 2-1. block diagram flash memory array i/o interface sck cs reset v cc gnd wp so si page (512/528 bytes) buffer 1 (512/528 bytes) buffer 2 (512/528 bytes) note: i/o 3-0 pin naming convention is used for dual-i/o and quad-i/o commands. (i/o 0 ) (i/o 3 ) (i/o 2 ) (i/o 1 )
6 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 3. memory array to provide optimal flexibility, the at45dq161 memory arra y is divided into three levels of granularity comprising of sectors, blocks, and pages. figure 3-1, memory architecture diagram illustrates the breakdown of each level and details the number of pages per sector and block. program operations to the dataflash can be done at the full page level or at the byte level (a variable number of bytes). the erase operations can be performed at the chip, sector, block, or page level. figure 3-1. memory architecture diagram sector 0a = 8 pages 4,096/4,224 bytes sector 0b = 248 pages 126,976/130,944 bytes block = 4,096/4,224 bytes 8 pages sector 0a sector 0b page = 512/528 bytes page 0 page 1 page 6 page 7 page 8 page 9 page 4,094 page 4,095 block 0 page 14 page 15 page 16 page 17 page 18 block 1 sector architecture block architecture page architecture block 0 block 1 block 30 block 31 block 32 block 33 block 510 block 511 block 62 block 63 block 64 block 65 sector 1 sector 2 sector 15 = 256 pages 131,072/135,168 bytes block 2 sector 1 = 256 pages 131,072 /135,168 bytes sector 14 = 256 pages 131,072/135,168 bytes sector 2 = 256 pages 131,072/135,168 bytes
7 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 4. device operation the device operation is controlled by instructions from the host processor. the list of instructions and their associated opcodes are contained in table 15- 1 on page 47 through table 15-4 on page 48. a valid instruction starts with the falling edge of cs followed by the appropriate 8-bit opcode and the desired buffer or main memory address location. while the cs pin is low, toggling the sck pin controls the loading of the opcode and the desired buffer or main memory address location through the si (serial input) pin. all instructions, addresses, and data are transferred with the most significant bit (msb) first. three address bytes are used to address memory locations in either the main memory array or in one of the sram buffers. the three address bytes will be comprised of a num ber of dummy bits and a number of actual device address bits, with the number of dummy bits varying depending on the operation being performed and the selected device page size. buffer addressing for the standard dataflash page size (528 bytes) is referenced in the datasheet using the terminology bfa9 - bfa0 to denote the 10 address bits requi red to designate a byte address within a buffer. the main memory addressing is referenced using the terminology pa11 - pa0 and ba9 - ba0, where pa11 - pa0 denotes the 12 address bits required to designate a page address, and ba9 - ba0 denotes the 10 address bits required to designate a byte address within the page. therefore, when using t he standard dataflash page size, a total of 22 address bits are used. for the ?power of 2? binary page size (512 bytes), the buffer addressing is referenced in the datasheet using the conventional terminology bfa8 - bfa0 to denote the 9 address bits required to designate a byte address within a buffer. main memory addressing is referenced using the terminology a20 - a0, where a20 - a9 denotes the 12 address bits required to designate a page address, and a8 - a0 denotes t he 9 address bits required to designate a byte address within a page. therefore, when using the binary page size, a total of 21 address bits are used. 4.1 dual-i/o and quad i/o operation the at45dq161 features a dual-input buffer write mode and a d ual-output read mode that allows two bits of data to be clocked into buffer 1 or buffer 2 or allows two bits of data to be read out of the device on every clock cycle to improve throughputs. to accomplish this, both the si and so pins are utilized as inputs/outputs for the transfer of data bytes. with the dual-input buffer write command, the so pin becomes an input along with the si pin. alternatively, with the dual- output read array command, the si pin becomes an output along with the so pin. for both dual-i/o commands, the so pin will be referrred to as i/o 1 and the si pin will be referred to as i/o 0 . the device also supports a quad-input buffer write mode and a quad-output read mode in which the wp and reset pins become data pins for even higher throughputs by allowing four bits of data to be clocked on every clock cycle into one of the buffers or by allowing four bits of data to be read out of the device on every clock cycle. for the quad-input buffer write and quad-output read array commands, the reset , wp , so and si pins are referred to as i/o 3-0 where reset becomes i/o 3 , wp becomes i/o 2 , so becomes i/o 1 and si becomes i/o 0 . the qe bit in the configuration register must be set (via issuing the quad enable command) to enable the quad-i/o operation and to enable the reset and wp pins to be converted to i/o data pins.
8 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 5. read commands by specifying the appropriate opcode, data can be read from t he main memory or from either one of the two sram data buffers. the dataflash supports rapids protocols for m ode 0 and mode 3. please see section 25., detailed bit- level read waveforms: rapids mode 0/mode 3 diagrams in th is datasheet for details on the clock cycle sequences for each mode. 5.1 continuous array read (legacy command: e8h opcode) by supplying an initial starting address fo r the main memory array, the continuous array read command can be utilized to sequentially read a continuous stream of data from the device by simply providing a clock signal; no additional addressing information or control signals need to be provided. the dataflash incorporates an internal address counter that will automatically increment on every clock cycle, allowing one continuous read from memory to be performed without the need for additional address sequences. to perform a conti nuous array read using the standard dataflash page size (528 bytes), an opcode of e8h must be cloc ked into the device followed by three address bytes (which comprise the 22-bit page and byte address sequence) and 4 dummy bytes. the firs t 12 bits (pa11 - pa0) of the 22-bit address sequence specify which page of the main memory array to read and t he last 10 bits (ba9 - ba0) of the 22-bit address sequence specify the starting byte address within the page. to per form a continuous array read using the binary page size (512 bytes), an opcode of e8h must be clocked into the dev ice followed by three address bytes and four dummy bytes. the first 12 bits (a20 - a9) of the 21-bit address sequence specify which page of the main memory array to read and the last nine bits (a8 - a0) of the 21-bit address sequence specify the starting byte address within the page. the dummy bytes that follow the address bytes are needed to initialize the read operation. following the dummy bytes, additional clock pulses on the sck pin will result in data being output on the so (serial output) pin. the cs pin must remain low during the loading of the opcode, the address bytes, the dummy bytes, and the reading of data. when the end of a page in the main memory is reached during a continuous array read, the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). when t he last bit in the main memory array has been read, the device will continue reading back at the beginning of the fi rst page of memory. as with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. a low-to-high transition on the cs pin will terminate the read operation and tri-state the output pin (so). the maximum sck frequency allowable for the conti nuous array read is defined by the f car1 specification. the continuous array read bypasses the data buffers and leaves the contents of the buffers unchanged. 5.2 continuous array read (high frequency mode: 1bh opcode) this command can be used to read the main memory array sequentially at the highest possible operating clock frequency up to the maximum specified by f car1 . to perform a continuous array read using the standard dataflash page size (528 bytes), the cs pin must first be asserted, and then an opcode of 1bh must be clocked into the device followed by three address bytes and two dummy bytes. the first 12 bits (pa11 - pa0) of the 22-bit address sequence specify which page of the main memory array to read and the last 10 bits (ba9 - ba0) of the 22-bit address sequence specify the starting byte address within the page. to per form a continuous array read using the binary page size (512 bytes), the opcode 1bh must be clocked into the device followed by three address bytes (a20 - a0) and two dummy bytes. following the dummy bytes, additional clock pulses on the sck pin will result in data being output on the so (serial output) pin. the cs pin must remain low during the loading of the opcode, the address bytes, the dummy bytes, and the reading of data. when the end of a page in the main memory is reached during a continuous array read, the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). when the last bit in the main memory array has been read, the device will continue reading back at the beginning of the first page of memory. as with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. a low-to-high transition on the cs pin will terminate the read operation and tri-state the output pin (so). the maximum sck frequency allowable for the conti nuous array read is defined by the f car1 specification. the continuous array read bypasses both data buffers and leaves the contents of the buffers unchanged.
9 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 5.3 continuous array read (high frequency mode: 0bh opcode) this command can be used to read the main memory array sequentially at higher clock frequencies up to the maximum specified by f car1 . to perform a continuous array read using the standard dataflash page size (528 bytes), the cs pin must first be asserted, and then an opcode of 0bh must be clocked into the device followed by three address bytes and one dummy byte. the first 12 bits (pa11 - pa0) of the 22- bit address sequence specify which page of the main memory array to read and the last 10 bits (ba9 - ba0) of the 22-bi t address sequence specify the starting byte address within the page. to perform a continuous array read using the binary page size (512 bytes), the opcode 0bh must be clocked into the device followed by three address bytes (a20 - a0) and one dummy byte. following the dummy byte, additional clock pulses on the sck pin will result in data being output on the so pin. the cs pin must remain low during the loading of the opcode, the address bytes, the dummy byte, and the reading of data. when the end of a page in the main memory is reached during a continuous array read, the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). when the last bit in the main memory array has been read, the device will continue reading back at the beginning of the first page of memory. as with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. a low-to-high transition on the cs pin will terminate the read operation and tri-state the output pin (so). the maximum sck frequency allowable for the conti nuous array read is defined by the f car1 specification. the continuous array read bypasses both data buffers and leaves the contents of the buffers unchanged. 5.4 continuous array read (low frequency mode: 03h opcode) this command can be used to read the main memory array sequentially at lower clock frequencies up to maximum specified by f car2 . unlike the previously described read commands, this continuous array read command for the lower clock frequencies does not require the clocking in of dummy bytes after the address byte sequence. to perform a continuous array read using the standard dataflash page size (528 bytes), the cs pin must first be asserted, and then an opcode of 03h must be clocked into the device followed by three address bytes. the first 12 bits (pa11 - pa0) of the 22-bit address sequence specify which page of the main memory array to read and the last 10 bits (ba9 - ba0) of the 22- bit address sequence specify the starting byte address within the page. to perform a continuous array read using the binary page size (512 bytes), the opcode 03h must be clocked into the device followed by three address bytes (a20 - a0). following the address bytes, additional clock pulses on t he sck pin will result in data being output on the so pin. the cs pin must remain low during the loading of the opcode, the address bytes, and the reading of data. when the end of a page in the main memory is reached during a continuous array read, the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). when the last bit in the main memory array has been read, the device will continue reading back at the beginning of the first page of memory. as with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. a low-to-high transition on the cs pin will terminate the read operation and tri-state the output pin (so). the maximum sck frequency allowable for the conti nuous array read is defined by the f car2 specification. the continuous array read bypasses both data buffers and leaves the contents of the buffers unchanged. 5.5 continuous array read (low power mode: 01h opcode) this command is ideal for applications that want to mi nimize power consumption and do not need to read the memory array at high frequencies. like the 03h opcode, this cont inuous array read command allows reading the main memory array sequentially without the need for dummy bytes to be clocked in after the address byte sequence. the memory can be read at clock frequencies up to maximum specified by f car3 . to perform a continuous array read using the standard dataflash page size (528 bytes), the cs pin must first be asserted, and then an opcode of 01h must be clocked into the device followed by three address bytes. the first 12 bits (pa11 - pa0) of the 22-bit address sequence specify which page of the main memory array to read and the last 10 bits (ba9 - ba0) of the 22-bit address sequence specify the starting byte address within the page. to perform a continuous arra y read using the binary page size (512 bytes), the opcode 01h must be clocked into the device followed by three address bytes (a20 - a0). following the address bytes, additional clock pulses on the sck pin will result in data being output on the so pin.
10 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 the cs pin must remain low during the loading of the opcode, the address bytes, and the reading of data. when the end of a page in the main memory is reached during a continuous array read, the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). when the last bit in the main memory array has been read, the device will continue reading back at the beginning of the first page of memory. as with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. a low-to-high transition on the cs pin will terminate the read operation and tri-state the output pin (so). the maximum sck frequency allowable for the conti nuous array read is defined by the f car3 specification. the continuous array read bypasses both data buffers and leaves the contents of the buffers unchanged. 5.6 main memory page read a main memory page read allows the reading of data directly from a single page in the main memory, bypassing both of the data buffers and leaving the contents of the buffers unchanged. to start a page read using the standard dataflash page size (528 bytes), an opcode of d2h must be clocked into the device followed by three address bytes (which comprise the 22-bit page and byte address sequence) and 4 dummy bytes. the first 12 bits (pa11 - pa0) of the 22-bit address sequence specify the page in main memory to be read and the last 10 bits (ba9 - ba0) of the 22-bit address sequence specify the starting byte address within that page. to start a page read using the binary page size (512 bytes), the opcode d2h must be clocked into the device followed by th ree address bytes and four dummy bytes. the first 12 bits (a20 - a9) of the 21-bit address sequence specify which page of the main memory array to read, and the last nine bits (a8 - a0) of the 21-bit address sequence specify the starting by te address within that page. the dummy bytes that follow the address bytes are sent to initialize the read operation. following the dummy bytes, the additional pulses on sck result in data being output on the so (serial output) pin. the cs pin must remain low during the loading of the opcode, the address bytes, the dummy bytes, and the reading of data. unlike the continuous array read command, when the end of a page in main memory is reached, the device will continue reading back at the beginning of the same page rather than the beginning of the next page. a low-to-high transition on the cs pin will terminate the read operation and tri-state the output pin (so). the maximum sck frequency allowable for the main memory page read is defined by the f sck specification. the main memory page read bypasses both data buffers and leaves the contents of the buffers unchanged. 5.7 buffer read the sram data buffers can be accessed independently from t he main memory array, and utilizing the buffer read command allows data to be sequentially read directly from either one of the buffers. four opcodes, d4h or d1h for buffer 1 and d6h or d3h for buffer 2, can be used for the buffer read command. the use of each opcode depends on the maximum sck frequency that will be used to read data from the buffers. the d4h and d6h opcode can be used at any sck frequency up to the maximum specified by f max while the d1h and d3h opcode can be used for lower frequency read operations up to the maximum specified by f car2 . to perform a buffer read using the standard dataflash buffer size (528 bytes), the opcode must be clocked into the device followed by three address bytes comprised of 14 dummy bits and 10 buffer address bits (bfa9 - bfa0). to perform a buffer read using the binary buffer size (512 bytes) , the opcode must be clocked into the device followed by three address bytes comprised of 15 dummy bits and 9 buffer address bits (bfa8 - bfa0). following the address bytes, one dummy byte must be clocked into the device to initia lize the read operation if using opcodes d4h or d6h. the cs pin must remain low during the loading of the opcode, the address bytes, the dummy byte (if using opcodes d4h or d6h), and the reading of data. when the end of a buffer is reached, the device will continue reading back at the beginning of the buffer. a low-to-high transition on the cs pin will terminate the read operation and tri-state the output pin (so).
11 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 5.8 dual-output read array the dual-output read array command is similar to the continuous array read command and can be used to sequentially read a continuous stream of data from the device by simply providing the clock signal once the initial starting address has been specified. unlike the continuous a rray read command however, the dual-output read array command allows two bits of data to be clocked out of the device on every clock cycle rather than just one. the dual-output read array command can be used at any clock frequency up to the maximum specified by f sck . to perform a dual-output read array using the standard dataflash page size (528 bytes), the cs pin must first be asserted, and then an opcode of 3bh must be clocked into the device followed by three address bytes and one dummy byte. the first 12 bits (pa11 - pa0) of the 22-bit address sequence spec ify which page of the main memory array to read and the last 10 bits (ba9 - ba0) of the 22-bit address sequence specify the starting byte address within the page. to perform a dual-output read array using the binary page size (512 bytes), the opcode 3bh must be clocked into the device followed by three address bytes (a20 - a0) and one dummy byte. after the three address bytes and the dummy byte have been cl ocked in, additional clock cycles will result in data being output on both the i/o 1 and i/o 0 pins. the data is always output with the msb of a byte first, and the msb is always output on the i/o 1 pin. during the first clock cycle, bit seven of the first data byte will be output on the i/o 1 pin while bit six of the same data byte will be output on the i/o 0 pin. during the next clock cycle, bits five and four of the first data byte will be output on the i/o 1 and i/o 0 pins, respectively. the sequence continues with each byte of data being output after every four clock cycles. the cs pin must remain low during the loading of the opcode, the address bytes, the dummy byte, and the reading of data. when the end of a page in the main memory is reached during a dual-output read arra y the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). when the last bit in the main memory array has been read, the device will continue reading back at the beginning of the first page of memory. as with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. a low-to-high transition on the cs pin will terminate the read operation and tri-state both the i/o 1 and i/o 0 pins. the dual- output dual-output read array bypasses both data buffers and leaves the contents of the buffers unchanged. 5.9 quad-output read array the quad-output read array command is similar to the dual-output read array command and can be used to sequentially read a continuous stream of data from the device by simply providing the clock signal once the initial starting address has been specified. unlike the dual-output read array command however, the quad-output read array command allows four bits of data to be clocked out of the device on every clock cycle rather than two. note: the qe bit in the configuration register must be previously set in order for any quad-i/o command (i.e. quad-output read array command) to be enabled and for the reset and wp pins to be converted to i/o data pins. the quad-output read array command can be used at any clock frequency up to the maximum specified by f sck . to perform a quad-output read array using the standard dataflash page size (528 bytes), the cs pin must first be asserted, and then an opcode of 6bh must be clocked into the device followed by three address bytes and one dummy byte. the first 12 bits (pa11 - pa0) of the 22-bit address sequence specify which page of the main memory array to read and the last 10 bits (ba9 - ba0) of the 22-bit address sequence specify the starting byte address within the page. to perform a quad-output read array using the binary page size (512 bytes), the opcode 6bh must be clocked into the device followed by three address bytes (a20 - a0) and one dummy byte. after the three address bytes and the dummy byte have been cl ocked in, additional clock cycles will result in data being output on the i/o 3-0 pins. the data is always output with the msb of a byte first and the msb is always output on the i/o 3 pin. during the first clock cycle, bit seven of the first data byte will be output on the i/o 3 pin while bits six, five, and four of the same data byte will be output on the i/o 2 , i/o 1 , and i/o 0 pins, respectively. during the next clock cycle, bits three, two, one, and zero of the first data byte will be output on the i/o 3 , i/o 2 , i/o 1 and i/o 0 pins, respectively. the sequence continues with each byte of data being output after every two clock cycles.
12 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 the cs pin must remain low during the loading of the opcode, the address bytes, the dummy byte, and the reading of data. when the end of a page in the main memory is reached during a quad-output read array the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). when the last bit in the main memory array has been read, the device will continue reading back at the beginning of the first page of memory. as with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. a low-to-high transition on the cs pin will terminate the read operation and tri-state the i/o 3 , i/o 2 , i/o 1 and i/o 0 pins. the quad-output read array bypasses both data buffers and leaves the contents of the buffers unchanged. 6. program and erase commands 6.1 buffer write utilizing the buffer write command allows data clocked in from the si pin to be written directly into either one of the sram data buffers. to load data into a buffer using the standard dataflash buffer size (528 bytes), an opcode of 84h for buffer 1 or 87h for buffer 2 must be clocked into the device followed by three address bytes comprised of 14 dummy bits and 10 buffer address bits (bfa9 - bfa0). the 10 buffer address bits specify the first byte in the buffer to be written. to load data into a buffer using the binary buffer size (512 bytes), an opcode of 84h for buffer 1 or 87h for buffer 2, must be clocked into the device followed by 15 dummy bits and 9 buf fer address bits (bfa8 - bfa0 ). the 9 buffer address bits specify the first byte in the buffer to be written. after the last address byte has been clocked into the device, data can then be clocked in on subsequent clock cycles. if the end of the data buffer is reached, the device will wrap around back to the beginning of the buffer. data will continue to be loaded into the buffer until a low-to-high transition is detected on the cs pin. 6.2 dual-input buffer write the dual-input buffer write command is similar to the bu ffer write command and can be used to increase the data input into one of the sram buffers by allowing two bits of data to be clocked into the device on every clock cycle rather than just one. to load data into a buffer using the standard dataflash buffer size (528 bytes), an opcode of 24h for buffer 1 or 27h for buffer 2 must be clocked into the device followed by three address bytes comprised of 14 dummy bits and 10 buffer address bits (bfa9 - bfa0). the 10 buffer address bits specify the first byte in the buffer to be written. to load data into a buffer using the binary buffer size (512 bytes), an opcode of 24h for buffer 1 or 27h for buffer 2, must be clocked into the device followed by 15 dummy bits and 9 buf fer address bits (bfa8 - bfa0 ). the 9 buffer address bits specify the first byte in the buffer to be written. after the last address byte has been clocked into the device, data can then be clocked in on subsequent clock cycles. if the end of the data buffer is reached, the device will wrap around back to the beginning of the buffer. data will continue to be loaded into the buffer until a low-to-high transition is detected on the cs pin. 6.3 quad-input buffer write the quad-input buffer write command is similar to the buff er write command and can be used to significantly increase the data input into one of the sram buffers by allowing four bits of data to be clocked into the device on every clock cycle rather than just one. to load data into a buffer using the standard dataflash buffer size (528 bytes), an opcode of 44h for buffer 1 or 47h for buffer 2 must be clocked into the device followed by three address bytes comprised of 14 dummy bits and 10 buffer address bits (bfa9 - bfa0). the 10 buffer address bits specify the first byte in the buffer to be written.
13 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 to load data into a buffer using the binary buffer size (512 bytes), an opcode of 44h for buffer 1 or 47h for buffer 2, must be clocked into the device followed by 15 dummy bits and 9 buf fer address bits (bfa8 - bfa0 ). the 9 buffer address bits specify the first byte in the buffer to be written. after the last address byte has been clocked into the device, data can then be clocked in on subsequent clock cycles. if the end of the data buffer is reached, the device will wrap around back to the beginning of the buffer. data will continue to be loaded into the buffer until a low-to-high transition is detected on the cs pin. 6.4 buffer to main memory page program with built-in erase the buffer to main memory page program with built-in eras e command allows data that is stored in one of the sram buffers to be written into an erased or programmed page in the main memory array. it is not necessary to pre-erase the page in main memory to be written because this command will automatically erase the selected page prior to the program cycle. to perform a buffer to main memory page program with built-in erase using the standard dataflash page size (528 bytes), an opcode of 83h for buffer 1 or 86h for buffer 2 must be clocked into the device followed by three address bytes comprised of 2 dummy bits, 12 page address bits (pa11 - pa0) that specify the page in the main memory to be written, and 10 dummy bits. to perform a buffer to main memory page program with bu ilt-in erase using the binary page size (512 bytes), an opcode of 83h for buffer 1 or 86h for buffer 2 must be clocked into the device followed by three address bytes comprised of 3 dummy bits, 12 page address bits (a20 - a9) that specify the page in the main memory to be written, and 9 dummy bits. when a low-to-high transition occurs on the cs pin, the device will first erase the selected page in main memory (the erased state is a logic 1) and then program the data stored in the appropriate buffer into that same page in main memory. both the erasing and the programming of the page are internally self-timed and should take place in a maximum time of t ep . during this time, the rdy/busy bit in the status register will indicate that the device is busy. the device also incorporates an intelligent erase and program algorithm that can detect when a byte location fails to erase or program properly. if an erase or programming error arises, it will be indicated by the epe bit in the status register. 6.5 buffer to main memory page program without built-in erase the buffer to main memory page program without built-in erase command allows data that is stored in one of the sram buffers to be written into a pre-erased page in the main memory array. it is necessary that the page in main memory to be written be previously erased in or der to avoid programming errors. to perform a buffer to main memory page program without built-in erase using the standard dataflash page size (528 bytes), an opcode of 88h for buffer 1 or 89h for buffer 2 must be clocked into the device followed by three address bytes comprised of 2 dummy bits, 12 page address bits (pa11 - pa0) that specify the page in the main memory to be written, and 10 dummy bits. to perform a buffer to main memory page program using the binary page size (512 bytes), an opcode of 88h for buffer 1 or 89h for buffer 2 must be clocked into the device followed by three address bytes comprised of three dummy bits, 12 page address bits (a20 - a9) that specify the page in the main memory to be written, and 9 dummy bits. when a low-to-high transition occurs on the cs pin, the device will program the data stored in the appropriate buffer into the specified page in the main memory. the page in main memory that is being programmed must have been previously erased using one of the erase commands (page erase, block erase, sector erase, or chip erase). the programming of the page is internally self-timed and should take place in a maximum time of t p . during this time, the rdy/busy bit in the status register will indicate that the device is busy. the device also incorporates an intelligent programming algorit hm that can detect when a byte location fails to program properly. if a programming error arises, it will be i ndicated by the epe bit in the status register.
14 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 6.6 main memory page program th rough buffer with built-in erase the main memory page program through buffer with built-in erase command combines the buffer write and buffer to main memory page program with built-in erase operations into a single operation to help simplify application firmware development. with the main memory page program through buffer with built-in erase command, data is first clocked into either buffer 1 or buffer 2, the addressed page in memory is then automatically erased, and then the contents of the appropriate buffer are programmed into the just-erased main memory page. to perform a main memory page program through buffer using the standard dataflash page size (528 bytes), an opcode of 82h for buffer 1 or 85h for buffer 2 must first be clocked into the device followed by three address bytes comprised of 2 dummy bits, 12 page address bits (pa11 - pa0) that specify the page in the main memory to be written, and 10 buffer address bits (bfa9 - bfa0) that select the first byte in the buffer to be written. to perform a main memory page program through buffer using the binary page size (512 bytes), an opcode of 82h for buffer 1 or 85h for buffer 2 must first be clocked into the device followed by three address bytes comprised of three dummy bits, 12 page address bits (a20 - a9) that specify the page in the main memory to be written, and 9 buffer address bits (bfa8 - bfa0) that select the first byte in the buffer to be written. after all address bytes have been clocked in, the device will take data from the input pin (si) and store it in the specified data buffer. if the end of the buffer is reached, the device will wrap around back to the beginning of the buffer. when there is a low-to-high transition on the cs pin, the device will first erase the selected page in main memory (the erased state is a logic 1) and then program the data stored in the buffer into that main memory page. both the erasing and the programming of the page are internally self-timed and should take place in a maximum time of t ep . during this time, the rdy/busy bit in the status register will indicate that the device is busy. the device also incorporates an intelligent erase and programming algorithm that can detect when a byte location fails to erase or program properly. if an erase or pr ogram error arises, it will be indicated by the epe bit in the status register. 6.7 main memory byte/page program thr ough buffer 1 wit hout built-in erase the main memory byte/page program through buffer 1 without built-in erase command combines both the buffer write and buffer to main memory program without built-in erase ope rations to allow any number of bytes (1 to 512/528 bytes) to be programmed directly into previously erased locations in the main memory array. with the main memory byte/page program through buffer 1 without built-in erase command, data is first clocked into buffer 1, and then only the bytes clocked into the buffer are programmed into the pre-erased byte locations in main memory. multiple bytes up to the page size can be entered with one command sequence. to perform a main memory byte/page program through buffe r 1 using the standard dataflash page size (528 bytes), an opcode of 02h must first be clocked into the device followed by three address bytes comprised of 2 dummy bits, 12 page address bits (pa11 - pa0) that specify the page in the main memory to be written, and 10 buffer address bits (bfa9 - bfa0) that select the first byte in the buffer to be written. after all address bytes are clocked in, the device will take data from the input pin (si) and store it in buffer 1. any number of bytes (1 to 528) can be entered. if the end of the buffer is reached, then the device will wrap around back to the beginning of the buffer. to perform a main memory byte/page program through buffe r 1 using the binary page size (512 bytes), an opcode of 02h for buffer 1 using must first be clocked into the device followed by three address bytes comprised of three dummy bits, 12 page address bits (a20 - a9) that specify the page in the main memory to be written, and 9 buffer address bits (bfa8 - bfa0) that selects the first byte in the buffer to be written. after all address bytes are clocked in, the device will take data from the input pin (si) and store it in buffer 1. any number of bytes (1 to 512) can be entered. if the end of the buffer is reached, then the device will wrap around back to the beginning of the buffer. when using the binary page size, the page and buffer address bits correspond to a 21-bit logical address (a20-a0) in the main memory. after all data bytes have been clocked into the device, a low-to-high transition on the cs pin will start the program operation in which the device will program the data stored in buffer 1 into the main memory array. only the data bytes that were clocked into the device will be programmed into the main memory. example: if only two data bytes were clocked into the device, then only two bytes will be programmed into main memory and the remaining bytes in the memory page will remain in their previous state.
15 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 the cs pin must be deasserted on a byte boundary (multiples of eight bits); otherwise, the operation will be aborted and no data will be programmed. the programming of the data bytes is internally self-timed and should take place in a maximum time of t p (the program time will be a multiple of the t bp time depending on the number of bytes being programmed). during this time, the rdy/busy bit in the status register will indicate that the device is busy. the device also incorporates an intelligent programming algorit hm that can detect when a byte location fails to program properly. if a programming error arises, it will be i ndicated by the epe bit in the status register. 6.8 page erase the page erase command can be used to individually erase any page in the main memory array allowing the buffer to main memory page program without built-in erase command or the main memory byte/page program through buffer 1 command to be utilized at a later time. to perform a page erase with the standard dataflash page size (528 bytes), an opcode of 81h must be clocked into the device followed by three address bytes comprised of 2 dummy bits, 12 page address bits (pa11 - pa0) that specify the page in the main memory to be erased, and 10 dummy bits. to perform a page erase with the binary page size (512 bytes), an opcode of 81h must be clocked into the device followed by three address bytes comprised of three dummy bits, 12 page address bits (a20 - a9) that specify the page in the main memory to be erased, and 9 dummy bits. when a low-to-high transition occurs on the cs pin, the device will erase the selected page (the erased state is a logic 1). the erase operation is internally self-timed and should take place in a maximum time of t pe . during this time, the rdy/busy bit in the status register will indicate that the device is busy. the device also incorporates an intelligent erase algorithm t hat can detect when a byte location fails to erase properly. if an erase error arises, it will be indicated by the epe bit in the status register. 6.9 block erase the block erase command can be used to erase a block of eight pages at one time. this command is useful when needing to pre-erase larger amounts of memory and is more efficient than issuing eight separate page erase commands. to perform a block erase with the standard dataflash page size (528 bytes), an opcode of 50h must be clocked into the device followed by three address bytes comprised of 2 dummy bits, 9 page address bits (pa11 - pa3), and 13 dummy bits. the 9 page address bits are used to specify which block of eight pages is to be erased. to perform a block erase with the binary page size (512 bytes), an opcode of 50h must be clocked into the device followed by three address bytes comprised of three dummy bits, 9 page address bits (a20 - a12), and 12 dummy bits. the 9 page address bits are used to specify which block of eight pages is to be erased. when a low-to-high transition occurs on the cs pin, the device will erase the selected block of eight pages. the erase operation is internally self-timed and should take place in a maximum time of t be . during this time, the rdy/busy bit in the status register will indicate that the device is busy. the device also incorporates an intelligent erase algorithm t hat can detect when a byte location fails to erase properly. if an erase error arises, it will be indicated by the epe bit in the status register.
16 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 table 6-1. block erase addressing 6.10 sector erase the sector erase command can be used to individually erase any sector in the main memory. the main memory array is comprised of 17 sectors, and only one sector can be erased at a time. to perform an erase of sector 0a or sector 0b with the standard dataflash page size (528 bytes), an opcode of 7ch must be clocked into the device followed by three address bytes comprised of 2 dummy bits, 9 page address bits (pa11 - pa3), and 13 dummy bits. to perform a sector 1-15 erase, an opcode of 7ch must be clocked into the device followed by three address bytes comprised of 2 dummy bits, 4 page address bits (pa11 - pa8), and 18 dummy bits. to perform a sector 0a or sector 0b erase with the binar y page size (512 bytes), an opcode of 7ch must be clocked into the device followed by three address bytes comprised of three dummy bits, 9 page address bits (a20 - a12), and 12 dummy bits. to perform a sector 1-15 erase, an opcode of 7ch must be clocked into the device followed by 3 dummy bits, 4 page address bits (a20 - a17), and 17 dummy bits. the page address bits are used to specify any valid address location within the sector to be erased. when a low-to high transition occurs on the cs pin, the device will erase the selected sector. the erase operation is internally self-timed and should take place in a maximum time of t se . during this time, the rdy/busy bit in the status register will indicate that the device is busy. the device also incorporates an intelligent algorithm that can detect when a byte location fails to erase properly. if an erase error arises, it will be indicated by the epe bit in the status register. pa11/ a20 pa10/ a19 pa9/ a18 pa8/ a17 pa7/ a16 pa6/ a15 pa5/ a14 pa4/ a13 pa3/ a12 pa2/ a11 pa1/ a10 pa0/ a9 block 0 0 0 0 0 0 0 0 0 x x x 0 0 0 0 0 0 0 0 0 1 x x x 1 0 0 0 0 0 0 0 1 0 x x x 2 0 0 0 0 0 0 0 1 1 x x x 3 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 1 1 1 1 1 1 0 0 x x x 508 1 1 1 1 1 1 1 0 1 x x x 509 1 1 1 1 1 1 1 1 0 x x x 510 1 1 1 1 1 1 1 1 1 x x x 511
17 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 table 6-2. sector erase addressing 6.11 chip erase the chip erase command allows the entire main memory array to be erased can be erased at one time. to execute the chip erase command, a 4-byte command sequence of c7h, 94h, 80h, and 9ah must be clocked into the device. since the entire memory array is to be erased, no address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. after the last bit of the opcode sequence has been clocked in, the cs pin must be deasserted to start the erase process. the erase operation is internally self-timed and should take place in a time of t ce . during this time, the rdy/busy bit in the status register will indicate that the device is busy. the chip erase command will not affect sectors that are pr otected or locked down; the contents of those sectors will remain unchanged. only those sectors that are not protected or locked down will be erased. the wp pin can be asserted while the device is erasing, but protection will not be activated until the internal erase cycle completes. the device also incorporates an intelligent algorithm that can detect when a byte location fails to erase properly. if an erase error arises, it will be indicated by the epe bit in the status register. table 6-3. chip erase command figure 6-1. chip erase pa11/ a20 pa10/ a19 pa9/ a18 pa8/ a17 pa7/ a16 pa6/ a15 pa5/ a14 pa4/ a13 pa3/ a12 pa2/ a11 pa1/ a10 pa0/ a9 sector 0 0 0 0 0 0 0 0 0 x x x 0a 0 0 0 0 0 0 0 0 1 x x x 0b 0 0 0 1 x x x x x x x x 1 0 0 1 0 x x x x x x x x 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 1 0 0 x x x x x x x x 12 1 1 0 1 x x x x x x x x 13 1 1 1 0 x x x x x x x x 14 1 1 1 1 x x x x x x x x 15 command byte 1 byte 2 byte 3 byte 4 chip erase c7h 94h 80h 9ah c7h 94h 80h 9ah cs each transition represents eight bits
18 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 6.12 program/erase suspend in some code and data storage applications, it may not be possible for the system to wait the milliseconds required for the flash memory to complete a program or erase cycl e. the program/erase suspend command allows a program or erase operation in progress to a particular 128kb sector of the main memory array to be suspended so that other device operations can be performed. example: by suspending an erase operation to a particular sector, the system can perform functions such as a program or read operation within a different 128kb sect or. other device operations, such as read status register, can also be performed while a program or erase operation is suspended. to perform a program/erase suspend, an opcode of b0h must be clocked into the device. no address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. when the cs pin is deasserted, the program or erase operation currently in progress will be suspended within a time of t susp . one of the program suspend bits (ps1 or ps2) or the erase suspend bi t (es) in the status register will then be set to the logic 1 state. in addition, the rdy/busy bit in the status register will indicate that the device is ready for another operation. read operations are not allowed to a 128kb sector that has had its program or erase operation suspended. if a read is attempted to a suspended sector, then the device will output undefined data. therefore, when performing a continuous array read operation and the device's internal address c ounter increments and crosses the sector boundary to a suspended sector, the device will then start outputting undefined data continuously until the address counter increments and crosses a sector boundary to an unsuspended sector. a program operation is not allowed to a sector that has been erase suspended. if a program operation is attempted to an erase suspended sector, then the program operation will abort. during an erase suspend, a program operation to a different 128kb sector can be started and subsequently suspended. this results in a simultaneous erase suspend/program suspend condition and will be indicated by the states of both the es and ps1 or ps2 bits in the status register being set to a logic 1. if a reset command is performed, or if the reset pin is asserted while a sector is erase suspended, then the suspend operation will be aborted and the contents of the sector will be left in an undefined state. however, if a reset is performed while a page is program or erase suspended, the suspend operat ion will abort but only the contents of the page that was being programmed or erased will be undefined; the remaining pages in the 128kb sector will retain their previous contents.
19 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 table 6-4. operations allowed and not allowed during suspend command operation during program suspend in buffer 1 (ps1) operation during program suspend in buffer 2 (ps2) operation during erase suspend (es) read commands read array (all opcodes) allowed allowed allowed read buffer 1 (all opcodes) allowed allowed allowed read buffer 2 (all opcodes) allowed allowed allowed dual-output read array allowed allowed allowed quad-output read array allowed allowed allowed read configuration register allowed allowed allowed read status register allowed allowed allowed read manufacturer and device id allowed allowed allowed program and erase commands buffer 1 write not allowed allowed allowed buffer 2 write allowed not allowed allowed dual-input buffer 1 write not allowed allowed allowed dual-input buffer 2 write allowed not allowed allowed quad-input buffer 1 write not allowed allowed allowed quad-input buffer 2 write allowed not allowed allowed buffer 1 to memory program w/ erase not allowed not allowed not allowed buffer 2 to memory program w/ erase not allowed not allowed not allowed buffer 1 to memory program w/o erase not allowed not allowed allowed buffer 2 to memory program w/o erase not allowed not allowed allowed memory program through buffer 1 w/ erase not allowed not allowed not allowed memory program through buffer 2 w/ erase not allowed not allowed not allowed memory program through buffer 1 w/o erase not allowed not allowed allowed auto page rewrite not allowed not allowed not allowed page erase not allowed not allowed not allowed block erase not allowed not allowed not allowed sector erase not allowed not allowed not allowed chip erase not allowed not allowed not allowed protection and security commands enable sector protection not allowed not allowed not allowed disable sector protection not allowed not allowed not allowed erase sector protection register not allowed not allowed not allowed program sector protection register not allowed not allowed not allowed read sector protection register allowed allowed allowed sector lockdown not allowed not allowed not allowed read sector lockdown allowed allowed allowed freeze sector lockdown state not allowed not allowed not allowed program security register not allowed not allowed not allowed read security register allowed allowed allowed additional commands main memory to buffer 1 transfer not allowed allowed allowed main memory to buffer 2 transfer allowed not allowed allowed main memory to buffer 1 compare allowed allowed allowed main memory to buffer 2 compare allowed allowed allowed enter deep power-down not allowed not allowed not allowed resume from deep power-down not allowed not allowed not allowed enter ultra-deep power-down mode not allowed not allowed not allowed reset (via hardwa re or software) allowed allowed allowed
20 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 6.13 program/erase resume the program/erase resume command allows a suspended program or erase operation to be resumed and continue where it left off. to perform a program/erase resume, an opcode of d0h must be clocked into the device. no address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. when the cs pin is deasserted, the program or erase operation currently suspended will be resumed within a time of t res . the ps1 bit, ps2 bit, or es bit in the status register will then be reset back to a logic 0 state to indicate that the program or erase operation is no longer suspended. in addition, the rdy/busy bit in the status register will indicate that the device is busy performing a program or erase operation. during a simultaneous erase suspend/program suspend conditi on, issuing the program/erase resume command will result in the program operation resuming first. after the program operation has been completed, the program/erase resume command must be issued again in order for the erase operation to be resumed. while the device is busy resuming a program or erase operat ion, any attempts at issuing the program/erase suspend command will be ignored. therefore, if a resumed progr am or erase operation needs to be subsequently suspended again, the system must either wait the entire t res time before issuing the program/erase suspend command, or it must check the status of the rdy/busy bit or the appropriate ps1, ps2, or es bit in the status register to determine if the previously suspended program or erase operation has resumed.
21 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 7. sector protection two protection methods, hardware and software controlled, are provided for protection agai nst inadvertent or erroneous program and erase cycles. the software controlled method relies on the use of software commands to enable and disable sector protection while the hardware controlled method employs the use of the write protect (wp ) pin. the selection of which sectors that are to be protected or unprotected against program and erase operations is specified in the nonvolatile sector protection register. the status of whether or not sector protection has been enabled or disabled by either the software or the hardware controlled met hods can be determined by checking the status register. 7.1 software sector protection software controlled protection is useful in applications in which the wp pin is not or cannot be controlled by a host processor. in such instances, the wp pin may be left floating (the wp pin is internally pulled high) and sector protection can be controlled using the enable sector protection and disable sector protection commands. if the device is power cycled, then the software controlled protection will be disabled. once the device is powered up, the enable sector protection command should be reissued if sector protection is desired and if the wp pin is not used. 7.1.1 enable sector protection sectors specified for protection in the sector protection r egister can be protected from program and erase operations by issuing the enable sector protection command. to enable th e sector protection, a 4-byte command sequence of 3dh, 2ah, 7fh, and a9h must be clocked into the device. after the last bit of the opcode sequence has been clocked in, the cs pin must be deasserted to enable the sector protection. table 7-1. enable sector protection command figure 7-1. enable sector protection command byte 1 byte 2 byte 3 byte 4 enable sector protection 3dh 2ah 7fh a9h 3dh 2ah 7fh a9h cs each transition represents eight bits si
22 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 7.1.2 disable sector protection to disable the sector protection, a 4-byte command sequence of 3dh, 2ah, 7fh, and 9ah must be clocked into the device. after the last bit of the opcode sequence has been clocked in, the cs pin must be deasserted to disable the sector protection. table 7-2. disable sector protection command figure 7-2. disable sector protection 7.2 hardware contro lled protection sectors specified for protection in the sector protection register and the sector protection register itself can be protected from program and erase operations by asserting the wp pin and keeping the pin in its asserted state. the sector protection register and any sector specified for protection cannot be erased or programmed as long as the wp pin is asserted. in order to modify the sector protection register, the wp pin must be deasserted. if the wp pin is permanently connected to gnd, then the contents of the sector protection register cannot be changed. if the wp pin is deasserted or permanently connected to v cc , then the contents of the sector protection register can be modified. the wp pin will override the software controlled protection method but only for protecting the sectors. example: if the sectors were not previously protected by the enable sector protection command, then simply asserting the wp pin would enable the sector protection within the maximum specified t wpe time. when the wp pin is deasserted, however, the sector protection would no longer be enabled (after the maximum specified t wpd time) as long as the enable sector protection command was not issued while the wp pin was asserted. if the enable sector protection command was issued before or while the wp pin was asserted, then simply deasserting the wp pin would not disable the sector protection. in this case, the disable sector protection command would need to be issued while the wp pin is deasserted to disable the sector protection. the disable sector protection command is also ignored whenever the wp pin is asserted. a noise filter is incorporated to help protect against spurious noise that may inadvertently assert or deassert the wp pin. figures 7-3 and table 7-3 detail the sector protection status for various scenarios of the wp pin, the enable sector protection command, and the disable sector protection command. command byte 1 byte 2 byte 3 byte 4 disable sector protection 3dh 2ah 7fh 9ah 3dh 2ah 7fh 9ah cs each transition represents eight bits si
23 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 figure 7-3. wp pin and protection status table 7-3. wp pin and protection status 7.3 sector protection register the nonvolatile sector protection register specifies which sectors are to be protected or unprotected with either the software or hardware controlled protection methods. the sector protection register contains 16 bytes of data, of which byte locations 0 through 15 contain values that specify whether sectors 0 through 15 will be protected or unprotected. the sector protection register is user modifiable and must be erased before it can be reprogrammed. table 7-4 illustrates the format of the sector protection register. table 7-4. sector protection register note: 1. the default values for bytes 0 through 15 are 00h when shipped from adesto. table 7-5. sector 0 (0a, 0b) sector protection register byte value note: 1. x = don?t care time period wp pin enable sector protection command disable sector protection command sector protection status sector protection register 1 high command not issued previously x disabled read/write ? issue command disabled read/write issue command ? enabled read/write 2 low x x enabled read 3 high command issued during period 1 or 2 not issued yet enabled read/write ? issue command disabled read/write issue command ? enabled read/write wp 12 3 sector number 0 (0a, 0b) 1 to 15 protected see table 7-5 ffh unprotected 00h bit 7:6 bit 5:4 bit 3:2 bit 1:0 data value sector 0a (page 0-7) sector 0b (page 8-255) n/a n/a sectors 0a and 0b unprotected 00 00 xx xx 0xh protect sector 0a 11 00 xx xx cxh protect sector 0b 00 11 xx xx 3xh protect sectors 0a and 0b 11 11 xx xx fxh
24 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 7.3.1 erase sector protection register in order to modify and change the values of the sector protec tion register, it must first be erased using the erase sector protection register command. to erase the sector protection register, a 4-byte command sequence of 3dh, 2ah, 7fh, and cfh must be clocked into the device. after the last bit of the opcode sequence has been clocked in, the cs pin must be deasserted to initiate the internally self-timed erase cycle. the erasing of the sector protection register should take place in a maximum time of t pe . during this time, the rdy/busy bit in the status register will indicate that the device is busy. if the device is powered-down before the completion of the erase cycle, then the contents of the sector protection register cannot be guaranteed. the sector protection register can be erased with sector protection enabled or disabled. since the erased state (ffh) of each byte in the sector protection register is used to indicate that a sector is specified for protection, leaving the sector protection enabled during the erasing of the register allows the protection scheme to be more effective in the prevention of accidental programming or erasing of the device. if for some reason an erroneous program or erase command is sent to the device immediately after erasing the sector protec tion register and before the register can be reprogrammed, then the erroneous program or erase command will not be processed because all sectors would be protected. table 7-6. erase sector protection register command figure 7-4. erase sector protection register 7.3.2 program sector protection register once the sector protection register has been erased, it can be reprogrammed using the program sector protection register command. to program the sector protection register, a 4-byte comma nd sequence of 3dh, 2ah, 7fh, and fch must be clocked into the device followed by 16 bytes of data corresponding to sectors 0 through 15. after the last bit of the opcode sequence and data have been clocked in, the cs pin must be deasserted to initiate the internally self-timed program cycle. the programming of the sector protection regist er should take place in a maximum time of t p . during this time, the rdy/busy bit in the status register will indicate that the dev ice is busy. if the device is powered-down before the completion of the erase cycle, then the contents of the sector protection register cannot be guaranteed. if the proper number of data bytes is not clocked in before the cs pin is deasserted, then the protection status of the sectors corresponding to the bytes not clocked in cannot be guaranteed. example: if only the first two bytes are clocked in instead of the complete 16 bytes, then the protection status of the last 14 sectors cannot be guaranteed. furthermore, if more than 16 bytes of data is clocked into the device, then the data will wrap back around to the beginning of the register. for instance, if 17 bytes of data are clocked in, then the 17th byte will be stored at byte location 0 of the sector protection register. the data bytes clocked into the sector protection register need to be valid values (0xh, 3xh, cxh, and fxh for sector 0a or sector 0b, and 00h or ffh for other sectors) in order fo r the protection to function correctly. if a non-valid value is command byte 1 byte 2 byte 3 byte 4 erase sector protection register 3dh 2ah 7fh cfh 3dh 2ah 7fh cfh cs each transition represents eight bits si
25 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 clocked into a byte location of the sector protection regist er, then the protection status of the sector corresponding to that byte location cannot be guaranteed. example: if a value of 17h is clocked into byte location 2 of the sector protection register, then the protection status of sector 2 cannot be guaranteed. the sector protection register can be reprogrammed while t he sector protection is enabled or disabled. being able to reprogram the sector protection register with the sector pr otection enabled allows the user to temporarily disable the sector protection to an individual sector rather than disabling sector protection completely. the program sector protection register command utilizes buffer 1 for processing. therefore, the contents of buffer 1 will be altered from its previous state when this command is issued. table 7-7. program sector protection register command figure 7-5. program sector protection register 7.3.3 read sector protection register to read the sector protection register, an opcode of 32h and three dummy bytes must be clocked into the device. after the last bit of the opcode and dummy bytes have been clocked in, any additional clock pulses on the sck pin will result in the sector protection register contents being output on the so pin. the first byte (byte location 0) corresponds to sector 0 (0a and 0b), the second byte corresponds to sector 1, and the last byte (byte location 15) corresponds to sector 15. once the last byte of the sector protection register has been clocked out, any additional clock pulses will result in undefined data being output on the so pin. the cs pin must be deasserted to terminate the read sector protection register operation and put the output into a high-impedance state. table 7-8. read sector protection register command note: 1. xx = dummy byte figure 7-6. read sector protection register command byte 1 byte 2 byte 3 byte 4 program sector protection register 3dh 2ah 7fh fch data byte n 3dh 2ah 7fh fch data byte n + 1 data byte n + 15 cs each transition represents eight bits si command byte 1 byte 2 byte 3 byte 4 read sector protection register 32h xxh xxh xxh 35h xx xx xx data n data n + 1 cs data n + 15 si so each transition represents eight bits
26 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 7.3.4 about the sector protection register the sector protection register is subject to a limit of 10,000 erase/program cycles. users are encouraged to carefully evaluate the number of times the sector protection register will be modified during the course of the application?s life cycle. if the application requires that the security protection register be modified more than the specified limit of 10,000 cycles because the application needs to temporarily unprotec t individual sectors (sector protection remains enabled while the sector protection register is reprogrammed), then the application will need to limit this practice. instead, a combination of temporarily unprotecting i ndividual sectors along with disabling sector protection completely will need to be implemented by the application to ensure that the limit of 10,000 cycles is not exceeded.
27 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 8. security features 8.1 sector lockdown the device incorporates a sector lockdown mechanism that allows each individual sector to be permanently locked so that it becomes read-only (rom). this is useful for applications that require the ability to permanently protect a number of sectors against malicious attempts at altering program code or security information. warning: once a sector is locked down, it can never be erased or programmed, and it can never be unlocked. to issue the sector lockdown command, a 4-byte command sequence of 3dh, 2ah, 7fh, and 30h must be clocked into the device followed by three address bytes specifying any address within the sector to be locked down. after the last address bit has been clocked in, the cs pin must be deasserted to initiate the internally self-timed lockdown sequence. the lockdown sequence should take place in a maximum time of t p . during this time, the rdy/busy bit in the status register will indicate that the device is busy. if the device is powered-down before the completion of the lockdown sequence, then the lockdown status of the sector cannot be guaranteed. in this case, it is recommended that the user read the sector lockdown register to determine the status of the appropriate sector lockdown bits or bytes and re-issue the sector lockdown command if necessary. table 8-1. sector lockdown command figure 8-1. sector lockdown 8.1.1 read sector lockdown register the nonvolatile sector lockdown register specifies which sectors in the main memory are currently unlocked or have been permanently locked down. the sector lockdown register is a read-only register and contains 16 bytes of data which correspond to sectors 0 through 15. to read the sector lockdown register, an opcode of 35h must be clocked into the device followed by three dummy bytes. after the last bit of the opcode and dummy bytes have been clocked in, the data for the contents of the sector lockdown register will be clocked out on the so pin. the first byte (byte location 0) corresponds to sector 0 (0a and 0b), the second byte corresponds to sector 1, and the last byte (byte location 15) corresponds to sector 15. after the last byte of the sector lockdown register has been read, additional pulses on the sck pin will result in undefined data being output on the so pin. deasserting the cs pin will terminate the read sector lockdown register operation and put the so pin into a high-impedance state. table 8-2 details the format the sector lockdown register. table 8-2. sector lockdown register command byte 1 byte 2 byte 3 byte 4 sector lockdown 3dh 2ah 7fh 30h 3dh 2ah 7fh 30h cs address byte address byte address byte si each transition represents eight bits sector number 0 (0a, 0b) 1 to 15 locked see table 8-3 ffh unlocked 00h
28 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 table 8-3. sector 0 (0a and 0b) sect or lockdown register byte value table 8-4. read sector lockdown register command figure 8-2. read sector lockdown register 8.1.2 freeze sector lockdown the sector lockdown command can be permanently disabled, and the current sector lockdown state can be permanently frozen so that no additional sectors can be lo cked down aside from those already locked down. any attempts to issue the sector lockdown command after the sector lockdown state has been frozen will be ignored. to issue the freeze sector lockdown command, the cs pin must be asserted and the opcode sequence of 34h, 55h, aah, and 40h must be clocked into the device. any additional data clocked into the device will be ignored. when the cs pin is deasserted, the current sector lockdown state will be permanently frozen within a time of t lock . in addition, the sle bit in the status register will be permanently reset to a logic 0 to indicate that the sector lockdown command is permanently disabled. table 8-5. freeze sector lockdown figure 8-3. freeze sector lockdown bit 7:6 bit 5:4 bit 3:2 bit 1:0 data value sector 0a (page 0-7) sector 0b (page 8-255) n/a n/a sectors 0a and 0b unlocked 00 00 00 00 00h sector 0a locked 11 00 00 00 c0h sector 0b locked 00 11 00 00 30h sectors 0a and 0b locked 11 11 00 00 f0h command byte 1 byte 2 byte 3 byte 4 read sector lockdown register 35h xxh xxh xxh 35h xx xx xx data n data n + 1 cs data n + 15 si so each transition represents eight bits command byte 1 byte 2 byte 3 byte 4 freeze sector lockdown 34h 55h aah 40h 34h 55h aah 40h cs si each transition represents eight bits
29 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 8.2 security register the device contains a specialized security register that c an be used for purposes such as unique device serialization or locked key storage. the register is comprised of a total of 128 bytes that is divided into two portions. the first 64 bytes (byte locations 0 through 63) of the security register are allocated as a one-time programmable space. once these 64 bytes have been programmed, they cannot be erased or reprogr ammed. the remaining 64 bytes of the register (byte locations 64 through 127) are factory programmed by adesto and will contain a unique value for each device. the factory programmed data is fixed and cannot be changed. table 8-6. security register 8.2.1 programming the security register the user programmable portion of the security regist er does not need to be erased before it is programmed. to program the security register, a 4-byte opcode sequence of 9bh, 00h, 00h, and 00h must be clocked into the device. after the last bit of the opcode sequence has been clocked into the device, the data for the contents of the 64-byte user programmable portion of the security register must be clocked in. after the last data byte has been clocked in, the cs pin must be deasserted to initiate the internally self-timed program cycle. the programming of the security register should take place in a time of t p , during which time the rdy/busy bit in the status register will indicate that the device is busy. if the device is powered-down during the program cycle, then the contents of the 64-byte user programmable porti on of the security register cannot be guaranteed. if the full 64 bytes of data are not clocked in before the cs pin is deasserted, then the values of the byte locations not clocked in cannot be guaranteed. example: if only the first two bytes are clocked in instead of the complete 64 bytes, then the remaining 62 bytes of the user programmable portion of the security register cannot be guaranteed. furthermore, if more than 64 bytes of data is clocked into the device, then the data will wrap back around to the beginning of the register. for example, if 65 bytes of data are clocked in, then the 65th byte will be stored at byte location 0 of the security register. warning: the user programmable portion of the security register can only be programmed one time. therefore, it is not possible, for example, to only pr ogram the first two bytes of the register and then program the remaining 62 bytes at a later time. the program security register command utilizes buffer 1 for processing. therefore, the contents of buffer 1 will be altered from its previous state when this command is issued. figure 8-4. program security register security register byte number 0 1 63 64 65 127 data type one-time user programmable factory programmed by adesto data n 9bh 00h 00h 00h data n + 1 data n + x cs si each transition represents eight bits
30 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 8.2.2 reading the security register to read the security register, an opcode of 77h and three dummy bytes must be clocked into the device. after the last dummy bit has been clocked in, the contents of the security register can be clocked out on the so pin. after the last byte of the security register has been read, additional pulses on the sck pin will result in undefined data being output on the so pin. deasserting the cs pin will terminate the read security register operation and put the so pin into a high-impedance state. figure 8-5. read security register 77h xx xx xx data n data n + 1 cs data n + x si so each transition represents eight bits
31 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 9. additional commands 9.1 main memory page to buffer transfer a page of data can be transferred from the main memory to eit her buffer 1 or buffer 2. to transfer a page of data using the standard dataflash page size (528 bytes), an opcode of 53h for buffer 1 or 55h for buffer 2 must be clocked into the device followed by three address bytes comprised of two du mmy bits, 12 page address bits (pa11 - pa0) which specify the page in main memory to be transferred, and 10 dummy bits. to transfer a page of data using the binary page size (512 bytes), an opcode of 53h for buffer 1 and 55h for buffer 2 must be clocked into the device followed by three address bytes comprised of three dummy bits, 12 page address bits (a20 - a9) which specify the page in the main memory to be transferred, and 9 dummy bits. the cs pin must be low while toggling the sck pin to load the opcode and the three address bytes from the input pin (si). the transfer of the page of data from the main memory to the buffer will begin when the cs pin transitions from a low to a high state. during the page transfer time (t xfr ), the rdy/busy bit in the status register can be read to determine whether or not the transfer has been completed. 9.2 main memory page to buffer compare a page of data in main memory can be compared to the data in buffer 1 or buffer 2 as a method to ensure that data was successfully programmed after a buffer to main memory page program command. to compare a page of data with the standard dataflash page size (528 bytes), an opcode of 60h for buffer 1 or 61h for buffer 2 must be clocked into the device followed by three address bytes comprised of two du mmy bits, 12 page address bits (pa11 - pa0) which specify the page in the main memory to be compared to the buffer, and 10 dummy bits. to compare a page of data with the binary page size (512 bytes), an opcode of 60h for buffer 1 or 61h for buffer 2 must be clocked into the device followed by three address bytes comprised of three dummy bits, 12 page address bits (a20 - a9) which specify the page in the main memory to be compared to the buffer, and 9 dummy bits. the cs pin must be low while toggling the sck pin to load the opcode and the address bytes from the input pin (si). on the low-to-high transition of the cs pin, the data bytes in the selected main memory page will be compared with the data bytes in buffer 1 or buffer 2. during the compare time (t comp ), the rdy/busy bit in the status register will indicate that the part is busy. on completion of the compare operation, bit 6 of the status register will be updated with the result of the compare. 9.3 auto page rewrite this command only needs to be used if the possibility exists that static (non-changing) data may be stored in a page or pages of a sector and the other pages of the same sect or are erased and programmed a large number of times. applications that modify data in a random fashion within a sect or may fall into this category. to preserve data integrity of a sector, each page within a sector must be updated/rewritten at least once within every 20,000 cumulative page erase/program operations within that sector. the auto page rewrite command provides a simple and efficient method to ?refresh? a page in the main memory array in a single operation. the auto page rewrite command is a combination of the main memory page to buffer transfer and buffer to main memory page program with built-in erase commands. with the auto page rewrite command, a page of data is first transferred from the main memory to buffer 1 or buffer 2 and then the same data (from buffer 1 or buffer 2) is programmed back into the same page of main memory, essentially ?refreshing? the contents of that page. to start the auto page rewrite operation with the standard dataflash page size (528 bytes), a 1-byte opcode, 58h for buffer 1 or 59h for buffer 2, must be clocked into the device followed by three address bytes comprised of two dummy bits, 12 page address bits (pa11-pa0) that specify the page in main memory to be rewritten, and 10 dummy bits. to initiate an auto page rewrite with the a binary page size ( 512 bytes), the opcode 58h for buffer 1 or 59h for buffer 2, must be clocked into the device followed by three address bytes consisting of three dummy bits, 12 page address bits (a20 - a9) that specify the page in the main memory that is to be rewritten, and 9 dummy bits. when a low-to-high transition occurs on the cs pin, the part will first transfer data from the page in main memory to a buffer and then
32 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 program the data from the buffer back into same page of main memory. the operation is internally self-timed and should take place in a maximum time of t ep . during this time, the rdy/busy status register will indicate that the part is busy. if a sector is programmed or reprogrammed sequentially page by page and the possibility does not exist that there will be a page or pages of static data, then the programming algorithm shown in figure 26-1 on page 71 is recommended. otherwise, if there is a chance that there may be a page or pages of a sector that will contain static data, then the programming algorithm shown in figure 26-2 on page 72 is recommended. please contact adesto for availability of devices that are specified to exceed the 20,000 cycle cumulative limit. 9.4 status register read the 2-byte status register can be used to determine the device's ready/busy status, page size, a main memory page to buffer compare operation result, the sector protection stat us, freeze sector lockdown status, erase/program error status, program/erase suspend status, and the device density. the status register can be read at any time, including during an internally self-timed program or erase operation. to read the status register, the cs pin must first be asserted and then the opcode d7h must be clocked into the device. after the opcode has been clocked in, the device will begin outputting status register data on the so pin during every subsequent clock cycle. after the second byte of the status register has been clocked out, the sequence will repeat itself, starting again with the first byte of the status register, as long as the cs pin remains asserted and the clock pin is being pulsed. the data in the status register is constantly being updated, so each repeating sequence may output new data. the rdy/busy status is available for both bytes of the status register and is updated for each byte. deasserting the cs pin will terminate the status register read operation and put the so pin into a high-impedance state. the cs pin can be deasserted at any time and does not require that a full byte of data be read. table 9-1. status register format ? byte 1 note: 1. r = readable only bit name type (1) description 7 rdy/busy ready/busy status r 0 device is busy with an internal operation. 1 device is ready. 6 comp compare result r 0 main memory page data matches buffer data. 1 main memory page data does not match buffer data. 5:2 density density code r 1011 16-mbit 1 protect sector protection status r 0 sector protection is disabled. 1 sector protection is enabled. 0 page size page size configuration r 0 device is configured for standard dataflash page size (528 bytes). 1 device is configured for ?power of 2? binary page size (512 bytes).
33 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 table 9-2. status register format ? byte 2 note: 1. r = readable only 9.4.1 rdy/busy bit the rdy/busy bit is used to determine whether or not an internal operat ion, such as a program or erase, is in progress. to poll the rdy/busy bit to detect the completion of an internally timed operation, new status register data must be continually clocked out of the device until the state of the rdy/busy bit changes from a logic 0 to a logic 1. 9.4.2 comp bit the result of the most recent main memory page to buffer compare operation is indicated using the comp bit. if the comp bit is a logic 1, then at least one bit of the data in the main memory page does not match the data in the buffer. 9.4.3 density bits the device density is indicated using the density bits. for the at45dq161, the four bit binary value is 1011. the decimal value of these four binary bits does not actually equate to the device density; the four bits represent a combinational code relating to differing densities of dataflash devices. the density bits are not the same as the density code indicated in the jedec device id informat ion. the density bits ar e provided only for backward compatibility to older generation dataflash devices. 9.4.4 protect bit the protect bit provides information to the user on whet her or not the sector protection has been enabled or disabled, either by the software-controlled method or the hardware-controlled method. 9.4.5 page size bit the page size bit indicates whether the buffer size and the page size of the main memory array is configured for the ?power of 2? binary page size (512 bytes) or the standard dataflash page size (528 bytes). bit name type (1) description 7 rdy/busy ready/busy status r 0 device is busy with an internal operation. 1 device is ready. 6 res reserved for future use r 0 reserved for future use. 5 epe erase/program error r 0 erase or program operation was successful. 1 erase or program error detected. 4 res reserved for future use r 0 reserved for future use. 3 sle sector lockdown enabled r 0 sector lockdown command is disabled. 1 sector lockdown command is enabled. 2 ps2 program suspend status (buffer 2) r 0 no program operation has been suspended while using buffer 2. 1 a sector is program suspended while using buffer 2. 1 ps1 program suspend status (buffer 1) r 0 no program operation has been suspended while using buffer 1. 1 a sector is program suspended while using buffer 1. 0 es erase suspend r 0 no sectors are erase suspended. 1 a sector is erase suspended.
34 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 9.4.6 epe bit the epe bit indicates whether the last erase or program operation completed successfully or not. if at least one byte during the erase or program operation did not erase or program properly, then the epe bit will be set to the logic 1 state. the epe bit will not be set if an erase or program operati on aborts for any reason, such as an attempt to erase or program a protected region or a locked down sector or an attempt to erase or program a suspended sector. the epe bit is updated after every erase and program operation. 9.4.7 sle bit the sle bit indicates whether or not the sector lockdown co mmand is enabled or disabled. if the sle bit is a logic 1, then the sector lockdown command is still enabled and sectors can be locked down. if the sle bit is a logic 0, then the sector lockdown command has been disabled and no further sectors can be locked down. 9.4.8 ps2 bit the ps2 bit indicates if a program operation has been suspended while using buffer 2. if the ps2 bit is a logic 1, then a program operation has been suspended while buffer 2 was being used, and any command attempts that would modify the contents of buffer 2 will be ignored. 9.4.9 ps1 bit the ps1 bit indicates if a program operation has been suspended while using buffer 1. if the ps1 bit is a logic 1, then a program operation has been suspended while buffer 1 was being used, and any command attempts that would modify the contents of buffer 1 will be ignored. 9.4.10 the es bit the es bit indicates whether or not an erase has been sus pended. if the es bit is a logic 1, then an erase operation (page, block, sector, or chip) has been suspended. 9.5 read configuration register the non-volatile configuration register can be used to determine if the quad-input buffer 1 or 2 write and quad-output read array commands have been enabled. unlike the status r egister, the configuration register can only be read when the device is in an idle state (when the rdy/ busy bit of the status register indicates that the device is in a ready state). to read the configuration register, the cs pin must first be asserted and the opcode of 3fh must be clocked into the device. after the opcode has been clocked in, the device will begin outputting one byte of configuration register data on the so pin during subsequent clock cycles. the data being output will be a repeating byte as long as the cs pin remains asserted and the clock pin is being pulsed. at clock frequencies above f clk , the first byte of data output will not be vali d. therefore, if operating at clock frequencies above f clk , at least two bytes of data must be clocked out from the device in order to determine the correct value of the configuration register. deasserting the cs pin will terminate the read configuration register operation and put the so pin into a high-impedance state. the cs pin can be deasserted at any time and does not require that a full byte of data be read. the configuration register is a non-volatile register; ther efore, the contents of the configuration register are not affected by power cycles or power-on reset operations.
35 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 figure 9-1. configuration register format note: 1. only bit seven of the configuration register will be modified when using the quad enable/disable commands. 9.5.1 qe bit the qe bit is used to control whether the quad-input buffer 1 write or buffer 2 write and the quad-output read array commands are enabled or disabled. when the qe bit is in the logical 1 state, the quad-input buffer write and quad- output read array commands are enabled and will be recognized by the device. in addition, the wp and reset functions are disabled and the wp and reset pins themselves operate as a bidirectional input/output pins (wp is i/o 2 and reset is i/o 3 ). when the qe bit is in the logical 0 state, the quad-input buffer write and quad-output read array commands are disabled and will not be recognized by the device as valid commands and the wp and reset pins function as normal control pins. the wp and reset pins should be externally pulled-high to avoid erroneous or unwanted device operation. the reset command has no effect on the qe bit. the qe bit defaults to the logical 0 state when devices are initially shipped from adesto. figure 9-2. read configuration register bit name type description 7 qe quad enable r/w 0 quad-input/output commands and operation disabled. 1 quad-input/output commands and operation enabled. (wp and reset disabled) 6:0 res reserved for future use r 0 reserved for future use. so si sck cs msb 23 1 0 00111111 67 5 41011 9 812 2122 17 20 19 18 15 16 13 14 23 24 opcode msb msb xxxxxx dx x d msb xxxxxx x d configuration register out configuration register out high-impedance
36 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 9.6 write configuration register the write configuration register commands are used to modify the qe bit of the non-volatile configuration register. there are two commands that are utilized to enable and disable the quad i/o functionality of the device and they are the quad enable and quad disable commands, respectively. the configuration register is a non-volatile register and is subject to the same program/erase endurance characteristics of the main memory array. the programming of the configurat ion register is internally self-timed and should take place in a time of t wrcr. while the configuration register is being updated, the status register can be read and will indicate that the device is busy. for faster throughput, it is recommended that the status register be polled rather than waiting the t wrcr time to determine if the configuration register has completed the programming cycle. 9.6.1 quad enable command the quad enable command is used to program the qe bit of t he non-volatile configuration register to a logical 1 to enable the quad i/o functionality of the device. to issue the quad enable command, the cs pin must first be asserted followed by a four byte opcode of 3dh, 2ah, 81h, and 66h. after the last bit of the four byte opcode has been clocked in, the cs pin must be deasserted allowing the qe bit of the configuration register to be modified within the time of t wrcr . table 9-3. quad enable command figure 9-3. quad enable command byte 1 byte 2 byte 3 byte 4 quad enable 3dh 2ah 81h 66h 3dh 2ah 81h 66h cs si each transition represents eight bits
37 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 9.6.2 quad disable command the quad disable command is used to program the qe bit of t he non-volatile configuration register to a logical 0 to disable the quad i/o functionality of the device. to issue the quad disable command, the cs pin must first be asserted followed by a four byte opcode of 3dh, 2ah, 81h and 67h. after the last bit of the four byte opcode has been clocked in, the cs pin must be deasserted allowing the qe bit of the configuration register to be modified within the time of t wrcr . table 9-4. quad disable command figure 9-4. quad disable command byte 1 byte 2 byte 3 byte 4 quad disable 3dh 2ah 81h 67h 3dh 2ah 81h 67h cs si each transition represents eight bits
38 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 10. deep power-down during normal operation, the device will be placed in the standby mode to consume less power as long as the cs pin remains deasserted and no internal operation is in progress. the deep power-down command offers the ability to place the device into an even lower power consumption state called the deep power-down mode. when the device is in the deep power-down mode, all co mmands including the status register read command will be ignored with the exception of the resume from deep power-down command. since all commands will be ignored, the mode can be used as an extra protection me chanism against program and erase operations. entering the deep power-down mode is accomplished by simply asserting the cs pin, clocking in the opcode b9h, and then deasserting the cs pin. any additional data clocked into the device after the opcode will be ignored. when the cs pin is deasserted, the device will enter the deep power-down mode within the maximum time of t edpd . the complete opcode must be clocked in before the cs pin is deasserted, and the cs pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and return to the standby mode once the cs pin is deasserted. in addition, the device will default to the standby mode after a power cycle. the deep power-down command will be ignored if an internally self-timed operation such as a program or erase cycle is in progress. the deep power-down command must be reissued after the internally self-timed operation has been completed in order for the device to enter the deep power-down mode. figure 10-1. deep power-down sck cs si so msb i cc 23 1 0 10111001 67 5 4 opcode high-impedance standby mode current active current deep power-down mode current t edpd
39 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 10.1 resume from deep power-down in order to exit the deep power-down mode and resume nor mal device operation, the resume from deep power-down command must be issued. the resume from deep power-down command is the only command that the device will recognize while in the deep power-down mode. to resume from the deep power-down mode, the cs pin must first be asserted and then the opcode abh must be clocked into the device. any additional data clocked into the device after the opcode will be ignored. when the cs pin is deasserted, the device will exit the deep power-down mode and return to the standby mode within the maximum time of t rdpd . after the device has returned to the standby mode, normal command operations such as continuous array read can be resumed. if the complete opcode is not clocked in before the cs pin is deasserted, or if the cs pin is not deasserted on an even byte boundary (multiples of eight bits), then the device will abort the operation and return to the deep power-down mode. figure 10-2. resume from deep power-down sck cs si so msb i cc 23 1 0 10101011 67 5 4 opcode high-impedance deep power-down mode current active current standby mode current t rdpd
40 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 10.2 ultra-deep power-down the ultra-deep power-down mode allows the device to consume far less power compared to the standby and deep power-down modes by shutting down additional internal circuitry. since almost all active circuitry is shutdown in this mode to conserve power, the contents of the sram buffers cannot be maintained. therefore, any data stored in the sram buffers will be lost once the devic e enters the ultra-deep power-down mode. when the device is in the ultra-deep power-down mode, all commands including the status register read and resume from deep power-down commands will be ignored. since all commands will be ignored, the mode can be used as an extra protection mechanism against program and erase operations. entering the ultra-deep power-down mode is accomplished by simply asserting the cs pin, clocking in the opcode 79h, and then deasserting the cs pin. any additional data clocked into the device after the opcode will be ignored. when the cs pin is deasserted, the device will enter the ultra- deep power-down mode within the maximum time of t eudpd . the complete opcode must be clocked in before the cs pin is deasserted, and the cs pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and return to the standby mode once the cs pin is deasserted. in addition, the device will default to the standby mode after a power cycle. the ultra-deep power-down command will be ignored if an inter nally self-timed operation such as a program or erase cycle is in progress. the ultra-deep power-down command must be reissued after the internally self-timed operation has been completed in order for the device to enter the ultra-deep power-down mode. figure 10-3. ultra -deep power-down sck cs si so msb i cc 23 1 0 0 67 5 4 opcode high-impedance ultra-deep power-down mode current active current standby mode current t eudpd 1111001
41 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 10.2.1 exit ultra- deep power-down to exit from the ultra-deep power-down mode, the cs pin must simply be pulsed by asserting the cs pin, waiting the minimum necessary t cslu time, and then deasserting the cs pin again. to facilitate simple software development, a dummy byte opcode can also be entered while the cs pin is being pulsed just as in a normal operation like the program suspend operation; the dummy byte opcode is simply ignored by the device in this case. after the cs pin has been deasserted, the device will exit from the ultra-deep po wer-down mode and return to the standby mode within a maximum time of t xudpd . if the cs pin is reasserted before the t xudpd time has elapsed in an attempt to start a new operation, then that operation will be ignored and nothing will be performed. the system must wait for the device to return to the standby mode before normal command operations such as continuous array read can be resumed. since the contents of the sram buffers cannot be maintained while in the ultra-deep power-down mode, the sram buffers will contain undefined data when the device returns to the standby mode. figure 10-4. exit ul tra-deep power-down cs so i cc high-impedance ultra-deep power-down mode current active current standby mode current t xudpd t cslu
42 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 11. buffer and page size configuration the memory array of dataflash devices is actually larger than other serial flash devices in that extra user-accessible bytes are provided in each page of the memory array. for the at45dq161, there are an extra 16 bytes of memory in each page for a total of an extra 64kb (512-kbits) of user-accessible memory. therefore, the device density is actually 16.5-mbits instead of 16-mbits. some applications, however, may not want to take advantage of this extra memory and instead architect their software to operate on a ?power of 2? binary, logical addressing scheme. to allow this, the dataflash can be configured so that the buffer and page sizes are 512 bytes instead of the standard 528 bytes. in addition, the configuration of the buffer and page sizes is reversible and can be changed from 528 bytes to 512 bytes or from 512 bytes to 528 bytes. the configured setting is stored in an internal nonvolatile register so that the buffer and page size configuration is not affected by power cycles. the nonvolatile register has a limit of 10,000 erase/progr am cycles; therefore, care should be taken to not switch between the size options more than 10,000 times. devices are initially shipped from adesto with the buffer and page sizes set to 528 bytes. devices can be ordered from adesto pre-configured for the ?power of 2? binary size of 512 bytes. for details, see section 27., ordering information on page 73. to configure the device for ?power of 2? binary page size (512 bytes), a 4-byte opcode sequence of 3dh, 2ah, 80h, and a6h must be clocked into the device. after the last bit of the opcode sequence has been clocked in, the cs pin must be deasserted to initiate the internally self-timed configuration process and nonvolatile register program cycle. the programming of the nonvolatile register should take place in a time of t ep , during which time the rdy/busy bit in the status register will indicate that the device is busy. the device does not need to be power cycled after the completion of the configuration process and register program cycle in order for the buffer and page size to be configured to 512 bytes. to configure the device for standard dataflash page size (528 bytes), a 4-byte opcode sequence of 3dh, 2ah, 80h, and a7h must be clocked into the device. after the last bit of the opcode sequence has been clocked in, the cs pin must be deasserted to initial the internally self-timed configur ation process and nonvolatile register program cycle. the programming of the nonvolatile register should take place in a time of t ep , during which time the rdy/busy bit in the status register will indicate that the device is busy. the device does not need to be power cycled after the completion of the configuration process and register pr ogram cycle in order for the buffer and page size to be configured to 528 bytes. table 11-1. buffer and page size configuration commands figure 11-1. buffer and page size configuration command byte 1 byte 2 byte 3 byte 4 ?power of 2? binary page size (512 bytes) 3dh 2ah 80h a6h dataflash page size (528 bytes) 3dh 2ah 80h a7h cs si 3dh 2ah 80h opcode byte 4 each transition represents eight bits
43 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 12. manufacturer an d device id read identification information can be read from the device to enable systems to electronically query and identify the device while it is in the system. the identification method and the command opcode comply with the jedec standard for ?manufacturer and device id read methodology for spi compatible serial interface memory devices?. the type of information that can be read from the device includes the jedec-defined manufacturer id, the vendor-specific device id, and the vendor-specific extended device information. the read manufacturer and device id command is limited to a maximum clock frequency of f clk . since not all flash devices are capable of operating at very high clock frequencies, applications should be designed to read the identification information from the devices at a reasonably lo w clock frequency to ensure that all devices to be used in the application can be identified properly. once the identification process is complete, the application can then increase the clock frequency to accommodate specific flash devices that are capable of operating at the higher clock frequencies. to read the identification information, the cs pin must first be asserted and then the opcode 9fh must be clocked into the device. after the opcode has been clocked in, the device will begin outputting the identification data on the so pin during the subsequent clock cycles. the first byte to be output will be the manufacturer id, followed by two bytes of the device id information. the fourth byte output will be the extended device information (edi) string length, which will be 01h indicating that one byte of edi data follows. after the one byte of edi data is output, the so pin will go into a high-impedance state; therefore, additional clock cycles will have no affect on the so pin and no data will be output. as indicated in the jedec standard, reading the ed i string length and any subsequent data is optional. deasserting the cs pin will terminate the manufacturer and device id read operation and put the so pin into a high-impedance state. the cs pin can be deasserted at any time and does not require that a full byte of data be read. table 12-1. manufacturer and device id information byte no. data type value 1 manufacturer id 1fh 2 device id (byte 1) 26h 3 device id (byte 2) 00h 4 [optional to read] extended device information (edi) string length 01h 5 [optional to read] edi byte 1 00h table 12-2. manufacturer and device id details data type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hex value details manufacturer id jedec assigned code 1fh jedec code: 0001 1111 (1fh for adesto) 0 0 0 1 1 1 1 1 device id (byte 1) family code density code 26h family code: 001 (at45dxxx family) density code: 00110 (16-mbit) 0 0 1 0 0 1 1 0 device id (byte 2) sub code product variant 00h sub code: 000 (standard series) product variant:00000 0 0 0 0 0 0 0 0
44 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 figure 12-1. read manufacturer and device id table 12-3. edi data byte number bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hex value details 1 rfu device revision 00h rfu: reserved for future use device revision:00000 (initial version) 0 0 0 0 0 0 0 0 sck cs si so 6 0 9fh 8 7 46 opcode 1fh 00h 01h 00h manufacturer id device id byte 1 device id byte 2 edi string length edi data byte 1 high-impedance 14 16 15 22 24 23 38 40 39 30 32 31 note: each transition shown for si and so represents one byte (8 bits) 26h
45 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 13. software reset in some applications, it may be necessary to prematurely terminate a program or erase cycle early rather than wait the hundreds of microseconds or milliseconds necessary for the program or erase operation to complete normally. the software reset command allows a program or erase operati on in progress to be ended abruptly and returns the device to an idle state. to perform a software reset, the cs pin must be asserted and a 4-byte command sequence of f0h, 00h, 00h, and 00h must be clocked into the device. any additional data clocked into the device after the last byte will be ignored. when the cs pin is deasserted, the program or erase operation currently in progress will be terminated within a time t swrst . since the program or erase operation may not complete before the device is reset, the contents of the page being programmed or erased cannot be guaranteed to be valid. the software reset command has no effect on the states of the sector protection register, the sector lockdown register, or the buffer and page size configuration. the ps2, ps1, and es bits of the status register, however, will be reset back to their default states. if a software reset operation is performed while a sector is erase suspended, the suspend operation will abort and the contents of the page or block being erased in the suspended sector will be left in an undefined state. if a software reset is performed while a sector is program suspended, the suspend operation will abort and the contents of the page that was being programmed and subsequently suspended will be undefined. the remaining pages in the sector will retain their previous contents. the complete 4-byte opcode must be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on a byte boundary (multiples of eight bits); otherwise, no reset operation will be performed. table 13-1. software reset figure 13-1. software reset command byte 1 byte 2 byte 3 byte 4 software reset f0h 00h 00h 00h cs si f0h 00h 00h 00h each transition represents eight bits
46 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 14. operation mode summary the commands described previously can be grouped into four different categories to better describe which commands can be executed at what times. group a commands consist of: 1. main memory page read 2. continuous array read (spi) 3. read sector protection register 4. read sector lockdown register 5. read security register 6. read configuration register group b commands consist of: 1. page erase 2. block erase 3. sector erase 4. chip erase 5. main memory page to buffer 1 (or 2) transfer 6. main memory page to buffer 1 (or 2) compare 7. buffer 1 (or 2) to main memory page program with built-in erase 8. buffer 1 (or 2) to main memory page program without built-in erase 9. main memory page program through buff er 1 (or 2) with built-in erase 10. main memory byte/page program through buffer 1 without built-in erase 11. auto page rewrite group c commands consist of: 1. buffer 1 (or 2) read 2. buffer 1 (or 2) write 3. status register read 4. manufacturer and device id read group d commands consist of: 1. erase sector protection register 2. program sector protection register 3. sector lockdown 4. program security register 5. buffer and page size configuration 6. freeze sector lockdown if a group a command is in progress (not fully completed), then another command in group a, b, c, or d should not be started. however, during the internally self-timed portion of group b commands, any command in group c can be executed. the group b commands using buffer 1 should use group c commands using buffer 2 and vice versa. finally, during the internally self-timed portion of a group d command, only the status register read command should be executed. most of the commands in group b can be suspended and resumed, except the buffer transfer, buffer compare, and auto page rewrite operations. if a group b command is suspended, all of the group a commands can be executed. see table 6-4 to determine which of the group b, group c, and group d commands are allowed.
47 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 15. command tables table 15-1. read commands table 15-2. program and erase commands command opcode main memory page read d2h continuous array read (low power mode) 01h continuous array read (low frequency) 03h continuous array read (high frequency) 0bh continuous array read (high frequency) 1bh dual-output read array 3bh quad-output read array 6bh continuous array read (legacy command ? not recommended for new designs) e8h buffer 1 read (low frequency) d1h buffer 2 read (low frequency) d3h buffer 1 read (high frequency) d4h buffer 2 read (high frequency) d6h command opcode buffer 1 write 84h buffer 2 write 87h dual-input buffer 1 write 24h dual-input buffer 2 write 27h quad-input buffer 1 write 44h quad-input buffer 2 write 47h buffer 1 to main memory page program with built-in erase 83h buffer 2 to main memory page program with built-in erase 86h buffer 1 to main memory page program without built-in erase 88h buffer 2 to main memory page program without built-in erase 89h main memory page program through buffer 1 with built-in erase 82h main memory page program through buffer 2 with built-in erase 85h main memory byte/page program through buffer 1 without built-in erase 02h page erase 81h block erase 50h sector erase 7ch chip erase c7h + 94h + 80h + 9ah program/erase suspend b0h program/erase resume d0h
48 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 table 15-3. protection and security commands table 15-4. additional commands command opcode enable sector protection 3dh + 2ah + 7fh + a9h disable sector protection 3dh + 2ah + 7fh + 9ah erase sector protection register 3dh + 2ah + 7fh + cfh program sector protection register 3dh + 2ah + 7fh + fch read sector protection register 32h sector lockdown 3dh + 2ah + 7fh + 30h read sector lockdown register 35h freeze sector lockdown 34h + 55h + aah + 40h program security register 9bh + 00h + 00h + 00h read security register 77h command opcode main memory page to buffer 1 transfer 53h main memory page to buffer 2 transfer 55h main memory page to buffer 1 compare 60h main memory page to buffer 2 compare 61h auto page rewrite through buffer 1 58h auto page rewrite through buffer 2 59h deep power-down b9h resume from deep power-down abh ultra-deep power-down 79h status register read d7h manufacturer and device id read 9fh read configuration register 3fh quad enable 3dh + 2ah + 81h + 66h quad disable 3dh + 2ah + 81h + 67h configure ?power of 2? (binary) page size 3dh + 2ah + 80h + a6h configure standard dataflash page size 3dh + 2ah + 80h + a7h software reset f0h + 00h + 00h + 00h
49 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 table 15-5. detailed bit-level addressing sequence for binary page size (512 bytes) note: x = dummy bit page size = 512 bytes address byte address byte address byte additional dummy bytes opcode opcode reserved reserved reserved a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 01h 0 0 0 0 0 0 0 1 x x x a a a a a a a a a a a a a a a a a a a a a n/a 02h 0 0 0 0 0 0 1 0 x x x a a a a a a a a a a a a a a a a a a a a a n/a 03h 0 0 0 0 0 0 1 1 x x x a a a a a a a a a a a a a a a a a a a a a n/a 0bh 0 0 0 0 1 0 1 1 x x x a a a a a a a a a a a a a a a a a a a a a 1 1bh 0 0 0 1 1 0 1 1 x x x a a a a a a a a a a a a a a a a a a a a a 2 24h 0 0 1 0 0 1 0 0 x x x x x x x x x x x x x x x a a a a a a a a a n/a 27h 0 0 1 0 0 1 1 1 x x x x x x x x x x x x x x x a a a a a a a a a n/a 32h 0 0 1 1 0 0 1 0 x x x x x x x x x x x x x x x x x x x x x x x x n/a 35h 0 0 1 1 0 1 0 1 x x x x x x x x x x x x x x x x x x x x x x x x n/a 3bh 0 0 1 1 1 0 1 1 x x x a a a a a a a a a a a a a a a a a a a a a 1 3fh 0 0 1 1 1 1 1 1 x x x x x x x x x x x x x x x x x x x x x x x x n/a 44h 0 1 0 0 0 1 0 0 x x x x x x x x x x x x x x x a a a a a a a a a n/a 47h 0 1 0 0 0 1 1 1 x x x x x x x x x x x x x x x a a a a a a a a a n/a 50h 0 1 0 1 0 0 0 0 x x x a a a a a a a a a x x x x x x x x x x x x n/a 53h 0 1 0 1 0 0 1 1 x x x a a a a a a a a a a a a x x x x x x x x x n/a 55h 0 1 0 1 0 1 0 1 x x x a a a a a a a a a a a a x x x x x x x x x n/a 58h 0 1 0 1 1 0 0 0 x x x a a a a a a a a a a a a x x x x x x x x x n/a 59h 0 1 0 1 1 0 0 1 x x x a a a a a a a a a a a a x x x x x x x x x n/a 60h 0 1 1 0 0 0 0 0 x x x a a a a a a a a a a a a x x x x x x x x x n/a 61h 0 1 1 0 0 0 0 1 x x x a a a a a a a a a a a a x x x x x x x x x n/a 6bh 0 1 1 0 1 0 1 1 x x x a a a a a a a a a a a a a a a a a a a a a 1 77h 0 1 1 1 0 1 1 1 x x x x x x x x x x x x x x x x x x x x x x x x n/a 79h 0 1 1 1 1 0 0 1 n/a n/a n/a n/a 7ch 0 1 1 1 1 1 0 0 x x x a a a a x x x x x x x x x x x x x x x x x n/a 81h 1 0 0 0 0 0 0 1 x x x a a a a a a a a a a a a x x x x x x x x x n/a 82h 1 0 0 0 0 0 1 0 x x x a a a a a a a a a a a a a a a a a a a a a n/a 83h 1 0 0 0 0 0 1 1 x x x a a a a a a a a a a a a x x x x x x x x x n/a 84h 1 0 0 0 0 1 0 0 x x x x x x x x x x x x x x x a a a a a a a a a n/a 85h 1 0 0 0 0 1 0 1 x x x a a a a a a a a a a a a a a a a a a a a a n/a 86h 1 0 0 0 0 1 1 0 x x x a a a a a a a a a a a a x x x x x x x x x n/a 87h 1 0 0 0 0 1 1 1 x x x x x x x x x x x x x x x a a a a a a a a a n/a 88h 1 0 0 0 1 0 0 0 x x x a a a a a a a a a a a a x x x x x x x x x n/a 89h 1 0 0 0 1 0 0 1 x x x a a a a a a a a a a a a x x x x x x x x x n/a 9fh 1 0 0 1 1 1 1 1 n/a n/a n/a n/a b9h 1 0 1 1 1 0 0 1 n/a n/a n/a n/a abh 1 0 1 0 1 0 1 1 n/a n/a n/a n/a b0h 1 0 1 1 0 0 0 0 n/a n/a n/a n/a d0h 1 1 0 1 0 0 0 0 n/a n/a n/a n/a d1h 1 1 0 1 0 0 0 1 x x x x x x x x x x x x x x x a a a a a a a a a n/a d2h 1 1 0 1 0 0 1 0 x x x a a a a a a a a a a a a a a a a a a a a a 4 d3h 1 1 0 1 0 0 1 1 x x x x x x x x x x x x x x x a a a a a a a a a n/a d4h 1 1 0 1 0 1 0 0 x x x x x x x x x x x x x x x a a a a a a a a a 1 d6h 1 1 0 1 0 1 1 0 x x x x x x x x x x x x x x x a a a a a a a a a 1 d7h 1 1 0 1 0 1 1 1 n/a n/a n/a n/a
50 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 table 15-6. detailed bit-level addressing sequence for standard dataflash page size (528 bytes) note: p = page address bit b = byte/buffer address bit x = dummy bit page size = 528-bytes address byte address byte address byte additional dummy bytes opcode opcode reserved reserved pa11 pa10 pa9 pa8 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 ba9 ba8 ba7 ba6 ba5 ba4 ba3 ba2 ba1 ba0 01h 0 0 0 0 0 0 0 1 x x p p p p p p p p p p p p b b b b b b b b b b n/a 02h 0 0 0 0 0 0 1 0 x x p p p p p p p p p p p p b b b b b b b b b b n/a 03h 0 0 0 0 0 0 1 1 x x p p p p p p p p p p p p b b b b b b b b b b n/a 0bh 0 0 0 0 1 0 1 1 x x p p p p p p p p p p p p b b b b b b b b b b 1 1bh 0 0 0 1 1 0 1 1 x x p p p p p p p p p p p p b b b b b b b b b b 2 24h 0 0 1 0 0 1 0 0 x x x x x x x x x x x x x x b b b b b b b b b b n/a 27h 0 0 1 0 0 1 1 1 x x x x x x x x x x x x x x b b b b b b b b b b n/a 32h 0 0 1 1 0 0 1 0 x x x x x x x x x x x x x x x x x x x x x x x x n/a 35h 0 0 1 1 0 1 0 1 x x x x x x x x x x x x x x x x x x x x x x x x n/a 3bh 0 0 1 1 1 0 1 1 x x p p p p p p p p p p p p b b b b b b b b b b 1 3fh 0 0 1 1 1 1 1 1 x x x x x x x x x x x x x x x x x x x x x x x x n/a 44h 0 1 0 0 0 1 0 0 x x x x x x x x x x x x x x x x x x x x x x x x n/a 47h 0 1 0 0 0 1 1 1 x x x x x x x x x x x x x x x x x x x x x x x x n/a 50h 0 1 0 1 0 0 0 0 x x p p p p p p p p p x x x x x x x x x x x x x n/a 53h 0 1 0 1 0 0 1 1 x x p p p p p p p p p p p p x x x x x x x x x x n/a 55h 0 1 0 1 0 1 0 1 x x p p p p p p p p p p p p x x x x x x x x x x n/a 58h 0 1 0 1 1 0 0 0 x x p p p p p p p p p p p p x x x x x x x x x x n/a 59h 0 1 0 1 1 0 0 1 x x p p p p p p p p p p p p x x x x x x x x x x n/a 60h 0 1 1 0 0 0 0 0 x x p p p p p p p p p p p p x x x x x x x x x x n/a 61h 0 1 1 0 0 0 0 1 x x p p p p p p p p p p p p x x x x x x x x x x n/a 6bh 0 1 1 0 1 0 1 1 x x p p p p p p p p p p p p b b b b b b b b b b 1 77h 0 1 1 1 0 1 1 1 x x x x x x x x x x x x x x x x x x x x x x x x n/a 79h 0 1 1 1 1 0 0 1 n/a n/a n/a n/a 7ch 0 1 1 1 1 1 0 0 x x p p p p x x x x x x x x x x x x x x x x x x n/a 81h 1 0 0 0 0 0 0 1 x x p p p p p p p p p p p p x x x x x x x x x x n/a 82h 1 0 0 0 0 0 1 0 x x p p p p p p p p p p p p b b b b b b b b b b n/a 83h 1 0 0 0 0 0 1 1 x x p p p p p p p p p p p p x x x x x x x x x x n/a 84h 1 0 0 0 0 1 0 0 x x x x x x x x x x x x x x b b b b b b b b b b n/a 85h 1 0 0 0 0 1 0 1 x x p p p p p p p p p p p p b b b b b b b b b b n/a 86h 1 0 0 0 0 1 1 0 x x p p p p p p p p p p p p x x x x x x x x x x n/a 87h 1 0 0 0 0 1 1 1 x x x x x x x x x x x x x x b b b b b b b b b b n/a 88h 1 0 0 0 1 0 0 0 x x p p p p p p p p p p p p x x x x x x x x x x n/a 89h 1 0 0 0 1 0 0 1 x x p p p p p p p p p p p p x x x x x x x x x x n/a 9fh 1 0 0 1 1 1 1 1 n/a n/a n/a n/a b9h 1 0 1 1 1 0 0 1 n/a n/a n/a n/a abh 1 0 1 0 1 0 1 1 n/a n/a n/a n/a b0h 1 0 1 1 0 0 0 0 n/a n/a n/a n/a d0h 1 1 0 1 0 0 0 0 n/a n/a n/a n/a d1h 1 1 0 1 0 0 0 1 x x x x x x x x x x x x x x b b b b b b b b b b n/a d2h 1 1 0 1 0 0 1 0 x x p p p p p p p p p p p p b b b b b b b b b b 4 d3h 1 1 0 1 0 0 0 1 x x x x x x x x x x x x x x b b b b b b b b b b n/a d4h 1 1 0 1 0 1 0 0 x x x x x x x x x x x x x x b b b b b b b b b b 1 d6h 1 1 0 1 0 1 1 0 x x x x x x x x x x x x x x b b b b b b b b b b 1 d7h 1 1 0 1 0 1 1 1 n/a n/a n/a n/a
51 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 16. power-on/reset state when power is first applied to the device, or when recoveri ng from a reset condition, the device will default to spi mode 3. in addition, the output pin (so) will be in a high impedance state, and a high-to-low transition on the cs pin will be required to start a valid instruction. the spi mode (mode 3 or mode 0) will be automatically selected on every falling edge of cs by sampling the inactive clock state. 16.1 initial power-up timing restrictions during power-up, the device must not be accessed for at least the minimum t vcsl time after the supply voltage reaches the minimum v cc level. while the device is being powered-up, the internal power-on reset (por) circuitry keeps the device in a reset mode until the supply voltage rises above the maximum por threshold value (v por ). during this time, all operations are disabled and the device will not respond to any commands. after power-up, the device will be in the standby mode. if the first operation to the device after power-up will be a program or erase operation, then the operation cannot be started until the supply voltage reaches the minimum v cc level and an internal device delay has elapsed. this delay will be a maximum time of t puw . table 16-1. power-up timing figure 16-1. power-up timing symbol parameter min max units t vcsl minimum v cc to chip select low time 70 s t puw power-up device delay before program or erase allowed 5 ms v por power-on reset (por) voltage 1.5 2.2 v program/erase operations permitted read operation permitted v cc v cc (min) v por (max) v por (min) time do not attempt device access during this time t puw t vcsl
52 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 17. system considerations the serial interface is controlled by the serial clock (sck), serial input (si), and chip select (cs ) pins. these signals must rise and fall monotonically and be free from noise. exce ssive noise or ringing on these pins can be misinterpreted as multiple edges and cause improper operation of the device. pcb traces must be kept to a minimum distance or appropriately terminated to ensure proper operation. if necessary, decoupling capacitors can be added on these pins to provide filtering against noise glitches. as system complexity continues to increase, voltage regulation is becoming more important. a key element of any voltage regulation scheme is its current sourcing capability. like all flash memories, the peak current for dataflash devices occurs during the programming and erasing operations. the supply voltage regulator needs to be able to supply this peak current requirement. an under specified regulator can cause current starvation. besides increasing system noise, current starvation during programming or erasing c an lead to improper operation and possible data corruption.
53 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 18. electrical specifications 18.1 absolute maximum ratings* 18.2 dc and ac operating range note: 1. see ordering codes. temperature under bias . . . . . . . . . . -55c to +125c storage temperature. . . . . . . . . . . . . -65c to +150c all input voltages (except v cc but including nc pins) with respect to ground . . . . . . . . . . . . -0.6v to +6.25v all output voltages with respect to ground . . . . . . . . .-0.6v to v cc + 0.6v *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. the ?absolute maximum ratings? ar e stress ratings only and functional operation of the device at these or any other conditions beyond those indicat ed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage extremes referenced in the ?absolute maximum ratings? are intended to accommodate short duration undershoot/overshoot conditions and does not imply or guarantee functional device operation at these levels for any extended period of time. at45dq161 2.3v version at45dq161 2.5v version operating temperature (case) industrial -40 ? c to 85 ? c -40 ? c to 85 ? c extended (1) 1. see ordering codes. -40 ? c to 105 ? c v cc power supply 2.3v to 3.6v 2.5v to 3.6v
54 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 18.3 dc characteristics notes: 1. typical values measured at 3.0v at 25 ? c. 2. i cc2 during a buffer read is 20ma maximum @ 20mhz. 3. all inputs (si, sck, cs , wp, and reset ) are guaranteed by design to be 5v toleran t. symbol parameter condition min typ max units i udpd ultra-deep power-down current all inputs at 0v or v cc 0.4 1 a i dpd deep power-down current cs , reset , wp = v ih all inputs at cmos levels 3 10 a i sb standby current cs , reset , wp = v ih all inputs at cmos levels 25 50 a i cc1 active current, low power read (01h) operation f = 1mhz; i out = 0ma; v cc = 3.6v 6 8 ma f = 10mhz; i out = 0ma; v cc = 3.6v 6.5 9 ma i cc2 (1)(2) active current, read operation f = 20mhz; i out = 0ma; v cc = 3.6v 11 14 ma f = 33mhz; i out = 0ma; v cc = 3.6v 12 16 ma f = 50mhz; i out = 0ma; v cc = 3.6v 13 19 ma f = 85mhz; i out = 0ma; v cc = 3.6v 16 26 ma i cc3 active current, program operation v cc = 3.6v 12 18 ma i cc4 active current, erase operation v cc = 3.6v 14 20 ma i li input load current all inputs at cmos levels 1 a i lo output leakage current all inputs at cmos levels 1 a v il input low voltage v cc x 0.3 v v ih input high voltage v cc x 0.7 v v ol output low voltage i ol = 1.6ma; v cc = 2.5v 0.4 v v oh output high voltage i oh = -100a v cc - 0.2v v
55 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 18.4 ac characteristics note: 1. values are based on device characterization, not 100% tested in production. symbol parameter at45dq161 2.3v version at45dq161 2.5v version min max min max units f max sck frequency 85 100 mhz f sck sck frequency 70 85 mhz f car1 sck frequency for continuous read 70 85 mhz f car2 sck frequency for continuous read (low frequency) 40 50 mhz f car3 sck frequency for continuous read (low power mode ? 01h opcode) 10 10 mhz t wh sck high time 6.4 5.2 ns t wl sck low time 6.4 5.2 ns t sckr (1) sck rise time, peak-to-peak 0.1 0.1 v/ns t sckf (1) sck fall time, peak-to-peak 0.1 0.1 v/ns t cs minimum cs high time 30 30 ns t css cs setup time 5 5 ns t csh cs hold time 5 5 ns t su data in setup time 2 2 ns t h data in hold time 1 1 ns t ho output hold time 0 0 ns t dis output disable time 8 6 ns t v output valid 8 6 ns t wpe wp low to protection enabled 1 1 s t wpd wp high to protection disabled 1 1 s t lock freeze sector lockdown time (from cs high) 200 200 s t eudpd cs high to ultra-deep power-down 3 3 s t cslu minimum cs low time to exit ultra-deep power-down 20 20 ns t xudpd exit ultra-deep power-down time 120 120 s t edpd cs high to deep power-down 3 3 s t rdpd resume from deep power-down time 35 35 s t xfr page to buffer transfer time 200 200 s t comp page to buffer compare time 220 220 s t rst reset pulse width 10 10 s t rec reset recovery time 1 1 s t swrst software reset time 30 30 s
56 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 18.5 program and er ase characteristics notes: 1. values are based on device characterization, not 100% tested in production. 2. not 100% tested (value guaranteed by design and characterization). 19. input test waveforms and measurement levels 20. output test load symbol parameter min typ max units t ep page erase and programming time (512/528 bytes) 15 40 ms t p page programming time 3 6 ms t bp byte programming time 8 s t pe page erase time 12 35 ms t be block erase time 45 100 ms t se sector erase time 1.4 3.5 s t ce chip erase time 22 40 s t susp suspend time program 10 20 s erase 20 40 t res resume time program 10 20 s erase 20 40 t otpp otp security register program time 200 500 s t wrcr write configuration register time 15 35 ms ac driving levels ac measurement level 0.1v cc v cc /2 0.9v cc t r , t f < 2ns (10% to 90%) device under test 30pf
57 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 21. utilizing the rapids function to take advantage of the rapids function's ability to operate at higher clock frequencies, a full clock cycle must be used to transmit data back and forth across the serial bus. the da taflash is designed to always clock its data out on the falling edge of the sck signal and clock data in on the rising edge of sck. for full clock cycle operation to be achieved, when the dataflash is clocking data out on the falling edge of sck, the host controller should wait until the next falling edge of sck to latch the data in. similarly, the host controller should clock its data out on the rising edge of sck in order to give the dataflash a full clock cycle to latch the incoming data in on the next rising edge of sck. figure 21-1. rapids mode sck mosi miso 1 234567 81 234567 8 mosi = master out, slave in miso = master in, slave out the master is the host controller and the slave is the dataflash. the master always clocks data out on the rising edge of sck and always clocks data in on the falling edge of sck. the slave always clocks data out on the falling edge of sck and always clocks data in on the rising edge of sck. a. master clocks out first bit of byte-mosi on the rising edge of sck b. slave clocks in first bit of byte-mosi on the next rising edge of sck c. master clocks out second bit of byte-mosi on the same rising edge of sck d. last bit of byte-mosi is clocked out from the master e. last bit of byte-mosi is clocked into the slave f. slave clocks out first bit of byte-so g. master clocks in first bit of byte-so h. slave clocks out second bit of byte-so i. master clocks in last bit of byte-so a b c d e f g 1 h byte-mosi msb lsb byte-so msb lsb slave cs i
58 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 figure 21-2. command sequence for read/write operations for page size 512 bytes (except status register read, manufacturer and devi ce id read, configuration register write and read) figure 21-3. command sequence for read/write operations for page size 528 bytes (except status register read, manufacturer and devi ce id read, configuration register write and read) si (input) cmd 8-bits 8-bits 8-bits page address (a20 - a9) x x x x x x x x x x x x x x x x lsb x x x x x x x x byte/buffer address (a8 - a0/bfa8 - bfa0) msb 3 dummy bits page address (pa11 - pa0) byte/buffer address (ba9 - ba0/bfa9 - bfa0) si (input) cmd 8-bits 8-bits 8-bits x x x x x x x x x x x x lsb x x x x x x x x msb 2 dummy bits x x x x
59 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 22. ac waveforms four different timing waveforms are shown in fi gure 22-1 through figure 22-4. waveform 1 shows the sck signal being low when cs makes a high-to-low transition and waveform 2 shows the sck signal being high when cs makes a high-to-low transition. in both cases, output so becomes valid while the sck signal is still lo w (sck low time is specified as t wl ). timing waveforms 1 and 2 conform to rapids serial interface but for frequencies up to 85mhz. waveforms 1 and 2 are compatible with spi mode 0 and spi mode 3, respectively. waveform 3 and 4 illustrate general timing diagram for rapids serial interface. these are similar to waveform 1 and 2, except that output so is not restricted to become valid during the t wl period. these timing waveforms are valid over the full frequency range (maximum frequency = 85mhz) of the rapids serial case. figure 22-1. waveform 1 = spi mode 0 compatible figure 22-2. waveform 2 = spi mode 3 compatible cs sck si so t css valid in t h t su t wh t wl t csh t cs t v high-impedance valid out t ho t dis high-impedance cs sck so t css valid in t h t su t wl t wh t csh t cs t v high z valid out t ho t dis high-impedance si
60 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 figure 22-3. waveform 3 = rapids mode 0 figure 22-4. waveform 4 = rapids mode 3 cs sck si so t css valid in t h t su t wh t wl t csh t cs t v high-impedance valid out t ho t dis high-impedance cs sck so t css valid in t h t su t wl t wh t csh t cs t v high z valid out t ho t dis high-impedance si
61 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 23. write operations the following block diagram and waveforms illu strate the various write sequences available. figure 23-1. block diagram figure 23-2. buffer write figure 23-3. dual- input buffer write flash memory array buffer 2 (512/528 bytes) i/o interface si (i/o 0 ) buffer 1 to main memory page program buffer 2 to main memory page program buffer 1 write buffer 2 write page (512/528 bytes) buffer 1 (512/528 bytes) cs si cmd xx xx, bfa9-8 bfa7-0 n n + 1 last byte completes writing into selected buffer binary page size 15 dummy bits + bfa8-bfa0 n = 1st byte read n+1 = 2nd byte read each transition represents eight bits sck msb msb 23 1 0 00100100 67 5 41011 9 812 39 37 38 33 36 35 34 31 32 29 30 opcode aaaa aaa aa msb msb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 address bits a23-a0 input data byte 1 msb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 input data byte n input data byte 2 high-impedance cs i/o 1 (so) i/o 0 (si)
62 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 figure 23-4. quad-input buffer write figure 23-5. buffer to main memory page program i/o 0 (si) sck i/o 1 (so) i/o 2 (wp) i/o 3 (reset) cs msb msb 23 1 0 01000100 67 5 41011 9 812 39 37 38 33 36 35 34 31 32 29 30 opcode aaaa aaa aa d 5 d 4 d 1 d 0 address bits a23-a0 high-impedance d 6 d 2 high-impedance msb msb msb msb d 7 d 3 d 5 d 4 d 1 d 0 d 6 d 2 d 7 d 3 d 5 d 4 d 1 d 0 d 6 d 2 d 7 d 3 d 5 d 4 d 1 d 0 d 6 d 2 d 7 d 3 d 5 d 4 d 1 d 0 d 6 d 2 d 7 d 3 msb high-impedance byte 1 in byte 2 in byte 3 in byte 4 in byte n in cs si (i/o 1 ) cmd xx,pa11-6 pa5-0, xx xx starts self-timed erase/program operation binary page size a20-a9 + 9 dummy bits each transition represents eight bits
63 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 24. read operations the following block diagram and waveforms illustrate the various read sequences available. figure 24-1. block diagram figure 24-2. main memory page read flash memory array page (512/528 bytes) buffer 2 (512/528 bytes) buffer 1 (512/528 bytes) i/o interface main memory page to buffer 1 main memory page to buffer 2 main memory page read buffer 1 read buffer 2 read so cs si (input) so (output) n cmd pa11-6 pa5-0, ba9-8 ba7-0 x x address for binary page size a20-a16 a15-a8 a7-a0 n n + 1 4 dummy bytes
64 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 figure 24-3. main memory page to buffer transfer data from the selected flash page is read into either sram buffer figure 24-4. buffer read cs si (input) cmd pa11-6 pa5-0, xx xxxx xx starts reading page data into buffer binary page size a20-a9 + 9 dummy bits so (output) cs si (input) so (output) n cmd x x... x, bfa9-8 bfa7-0 x address for binary page size a20-a16 a15-a8 a7-a0 n n + 1 no dummy byte (opcodes d1h and d3h) 1 dummy byte (opcodes d4h and d6h) each transition represents eight bits
65 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 25. detailed bit-level read wav eforms: rapids mode 0/mode 3 figure 25-1. continuous array read (legacy opcode e8h) figure 25-2. continuous array read (opcode 0bh) figure 25-3. continuous array read (opcode 01h or 03h) sck cs si so msb msb 2 3 1 0 1 1 1 0 1 0 0 0 6 7 5 4 10 11 9 8 12 63 66 67 65 64 62 33 34 31 32 29 30 68 71 72 70 69 opcode a a a a a a a a a msb x x x x x x msb msb d d d d d d d d d d address bits 32 dummy bits data byte 1 high-impedance bit 4095/4223 of page n bit 0 of page n+1 sck cs si so msb msb 2 3 1 0 0 0 0 0 1 0 1 1 6 7 5 4 10 11 9 8 12 39 42 43 41 40 38 33 34 31 32 29 30 44 47 48 46 45 opcode a a a a a a a a a msb x x x x x x msb msb d d d d d d d d d d address bits a20 - a0 dummy bits data byte 1 high-impedance 36 37 35 x x sck cs si so msb msb 2 3 1 0 0 0 0 0 0 0 1 1 6 7 5 4 10 11 9 8 12 37 38 33 36 35 34 31 32 29 30 39 40 opcode a a a a a a a a a msb msb d d d d d d d d d d address bits a20-a0 data byte 1 high-impedance
66 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 figure 25-4. main memory page read (opcode d2h) figure 25-5. dual-output read array (opcode 3bh) sck cs si so msb msb 2 3 1 0 1 1 0 1 0 0 1 0 6 7 5 4 10 11 9 8 12 63 66 67 65 64 62 33 34 31 32 29 30 68 71 72 70 69 opcode a a a a a a a a a msb x x x x x x msb msb d d d d d d d d d d address bits 32 dummy bits data byte 1 high-impedance sck cs i/o 0 (si) i/o 1 (so) msb msb 23 1 0 001 1 1011 67 5 41011 9 812 394243 41 40 38 33 34 31 32 29 30 44 47 48 46 45 opcode aaaa aaa aa msb xxxx xx msb msb d 3 d 1 d5 d 7 d 3 d 1 d5 d 7 d5 d 7 d 2 d 0 d 4 d 6 d 4 d 6 d 2 d 0 d 4 d 6 address bits a20 - a0 dummy bits output data byte 1 output data byte 2 high-impedance 36 37 35 x x
67 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 figure 25-6. quad-output read array (opcode 6bh) figure 25-7. buffer read (opcode d4h or d6h) sck cs i/o 0 (si) i/o 1 (so) msb msb 23 1 0 01 110 011 67 5 41011 9 812 394243 41 40 38 33 34 31 32 29 30 44 47 48 46 45 opcode aaaa aaa aa msb xxxx xx d 4 d 0 d 0 d 4 d 4 d 4 d 0 d 0 d 0 d 4 address bits a20 - a0 dummy bits byte 1 out byte 4 out byte 5 out byte 3 out byte 2 out high-impedance i/o 2 (wp) d 2 d 6 d 2 d 6 d 2 d 6 d 2 d 6 d 2 d 6 d 1 d 5 d 5 high-impedance i/o 3 ( reset ) msb msb msb msb msb d 7 d3 d 7 d3 d 7 d3 d 7 d3 d 7 d3 high-impedance 36 37 35 x x d 1 d 5 d 1 d 1 d 5 d 1 d 5 sck cs si so msb msb 2 3 1 0 1 1 0 1 0 1 0 0 6 7 5 4 10 11 9 8 12 39 42 43 41 40 37 38 33 36 35 34 31 32 29 30 44 47 48 46 45 opcode x x x x a a a x x msb x x x x x x x x msb msb d d d d d d d d d d address bits binary page size = 15 dummy bits + bfa8-bfa0 standard dataflash page size = 14 dummy bits + bfa9-bfa0 dummy bits data byte 1 high-impedance
68 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 figure 25-8. buffer read ? low frequency (opcode d1h or d3h) figure 25-9. read sector protection register (opcode 32h) figure 25-10.read sector lockdown register (opcode 35h) sck cs si so msb msb 2 3 1 0 1 1 0 1 0 0 0 1 6 7 5 4 10 11 9 8 12 37 38 33 36 35 34 31 32 29 30 39 40 opcode x x x x a a a x x msb msb d d d d d d d d d d data byte 1 high-impedance address bits binary page size = 15 dummy bits + bfa8-bfa0 standard dataflash page size = 14 dummy bits + ba9-bfa0 sck cs si so msb msb 2 3 1 0 0 0 1 1 0 0 1 0 6 7 5 4 10 11 9 8 12 37 38 33 36 35 34 31 32 29 30 39 40 opcode x x x x x x x x x msb msb d d d d d d d d d dummy bits data byte 1 high-impedance sck cs si so msb msb 2 3 1 0 0 0 1 1 0 1 0 1 6 7 5 4 10 11 9 8 12 37 38 33 36 35 34 31 32 29 30 39 40 opcode x x x x x x x x x msb msb d d d d d d d d d dummy bits data byte 1 high-impedance
69 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 figure 25-11.read securi ty register (opcode 77h) figure 25-12. status regi ster read (opcode d7h) figure 25-13. manufacturer and device read (opcode 9fh) sck cs si so msb msb 2 3 1 0 0 1 1 1 0 1 1 1 6 7 5 4 10 11 9 8 12 37 38 33 36 35 34 31 32 29 30 39 40 opcode x x x x x x x x x msb msb d d d d d d d d d dummy bits data byte 1 high-impedance sck cs si so msb 2 3 1 0 1 1 0 1 0 1 1 1 6 7 5 4 10 11 9 8 12 21 22 17 20 19 18 15 16 13 14 23 24 opcode msb msb d d d d d d d d d d msb d d d d d d d d status register data status register data high-impedance sck cs si so 6 0 9fh 8 7 46 opcode 1fh 00h 01h 00h manufacturer id device id byte 1 device id byte 2 edi string length edi data byte 1 high-impedance 14 16 15 22 24 23 38 40 39 30 32 31 note: each transition shown for si and so represents one byte (8 bits) 26h
70 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 figure 25-14.reset timing note: 1. the cs signal should be in the high state before the reset signal is deasserted. cs sck reset so (output) high impedance high impedance si (input) t rst t rec t css
71 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 26. auto page rewrite flowchart figure 26-1. algorithm for programming or re-p rogramming of the enti re array sequentially notes: 1. this type of algorithm is used for applications in which the entire array is programmed sequentially, filling the array page-by-page 2. a page can be written using either a main memory page program operation or a buffer write operation followed by a buffer to main memory page program operation 3. the algorithm above shows the programming of a si ngle page. the algorithm will be repeated sequentially for each page within the entire array start main memory page program through buffer (82h, 85h) end provide address and data buffer write (84h, 87h) buffer to main memory page program (83h, 86h)
72 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 figure 26-2. algorithm for programming or re -programming of the entire array randomly notes: 1. to preserve data integrity, each page of an dataflash sector must be updated/rewritten at least once within every 20,000 cumulative page erase and program operations 2. a page address pointer must be maintained to indicate which page is to be rewritten. the auto page rewrite command must use the address specified by the page address pointer 3. other algorithms can be used to rewrite portions of the flash array. low-power applications may choose to wait until 20,000 cumulative page erase and program operations have accumulated before rewriting all pages of the sector. see application note an-4 (?using adesto?s serial dataflash?) for more details start main memory page to buffer transfer (53h, 55h) increment page address pointer (2) auto page rewrite (2) (58h, 59h) end provide address of page to modify if planning to modify multiple bytes currently stored within a page of the flash array main memory page program through buffer (82h, 85h) buffer write (84h, 87h) buffer to main memory page program (83h, 86h)
73 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 27. ordering information 27.1 ordering detail device grade h = green, nipdau lead finish, industrial temperature range (?40c to +85c) u = green, matte sn or sn alloy, industrial temperature range (?40c to +85c) designator product family device density shipping carrier option package option 16 = 16-mbit interface 1 = serial 45dq = dataflash dual/quad i/o b = bulk (tubes) t = tape and reel y = trays binary page size option 2b = factory set 512 byte binary page size option operating voltage d = 2.5v minimum (2.5v to 3.6v) f = 2.3v minimum (2.3v to 3.6v) ss = 8-lead, 0.150? wide soic s = 8-lead, 0.208? wide soic m = 8-pad, 5 x 6 x 0.6mm udfn cc = 9-ball, 3 x 3 (1mm pitch) ubga at45dq161-sshd2b-b
74 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 27.2 ordering codes notes: 1. the shipping carrier suffix is not marked on the device. 2. not recommended for new design. use the 8s1 package option. ordering code package lead finish operating voltage f sck device grade at45dq161-sshd-b (1) 8s1 nipdau 2.5v to 3.6v 100mhz industrial (-40 ? c to 85 ? c) at45dq161-sshd-t (1) at45dq161-shd-b (1)(2) 8s2 at45dq161-shd-t (1)(2) at45dq161-mhd-y (1) 8ma1 AT45DQ161-MHD-T (1) at45dq161-ccud-t (1) 9cc1 snagcu at45dq161-sshf-b (1) 8s1 nipdau 2.3v to 3.6v 85mhz industrial (-40 ? c to 85 ? c) at45dq161-sshf-t (1) at45dq161-mhf-y (1) 8ma1 at45dq161-mhf-t (1) package type 8s1 8-lead 0.150" wide, plastic gull wing small outline (jedec soic) 8s2 8-lead 0.208" wide, plastic gull wing small outline (eiaj soic) 8ma1 8-pad (5 x 6 x 0.6mm body), thermally enhanced plastic ultra thin dual flat no-lead (udfn) 9cc1 9-ball (6 x 6 x 0.6mm body) 3 x 3 array x 1 mm pitch, ultra-thin ba ll grid array (ubga)
75 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 27.3 ordering codes (binary page mode) notes: 1. the shipping carrier suffix is not marked on the device. 2. not recommended for new design. use the 8s1 package option. 3. parts ordered with suffix code ?2b? are shipped in tape and reel (t&r) with the page size set to 512 bytes. this option is only available for shipping in t&r (-t). 27.4 ordering codes (extended temperature range) notes: 1. the shipping carrier suffix is not marked on the device. 2. not recommended for new design. use the 8s1 package option. 3. parts ordered with suffix code ?hb? are shipped in tape and reel (t&r) with the page size set to 512 bytes and configuration register quad enable (qe) bit7 set to '1' . 4. parts ordered with suffix code ?hd? are shipped in tape and reel (t&r) with the page size set to 528 bytes and configuration register quad enable (qe) bit7 set to '1' . ordering code package lead finish operating voltage f sck device grade at45dq161-sshd2b-t (1)(3) 8s1 nipdau 2.5v to 3.6v 100mhz industrial (-40 ? c to 85 ? c) at45dq161-shd2b-t (1)(2)(3) 8s2 at45dq161-mhd2b-t (1)(3) 8ma1 at45dq161-sshf2b-t (1)(3) 8s1 nipdau 2.3v to 3.6v 85mhz industrial (-40 ? c to 85 ? c) at45dq161-mhf2b-t (1)(3) 8ma1 ordering code package lead finish operating voltage f sck device grade at45dq161-sshfhb-t (1)(3) 8s1 nipdau 2.3v to 3.6v 85mhz industrial (-40 ? c to 105 ? c) at45dq161-shfhb-t (1)(2)(3) 8s2 at45dq161-sshfhd-b (1)(4) 8s1 nipdau 2.3v to 3.6v 85mhz industrial (-40 ? c to 105 ? c) at45dq161-shfhd-t (1)(4) 8s2 package type 8s1 8-lead 0.150" wide, plastic gull wing small outline (jedec soic) 8s2 8-lead 0.208" wide, plastic gull wing small outline (eiaj soic) 8ma1 8-pad (5 x 6 x 0.6mm body), thermally enhanced plastic ultra thin dual flat no-lead (udfn)
76 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 28. packaging information 28.1 8s1 ? 8-lead jedec soic drawing no. rev. title gpc common dimensions (unit of measure = mm) symbol min nom max note a1 0.10 ? 0.25 a 1.35 ? 1.75 b 0.31 ? 0.51 c 0.17 ? 0.25 d 4.80 ? 5.05 e1 3.81 ? 3.99 e 5.79 ? 6.20 e 1.27 bsc l 0.40 ? 1.27 ? ? 0 ? 8 ? e 1 n top view c e1 end view a b l a1 e d side view package drawing contact: contact@adestotech.com 8s1 g 6/22/11 notes: this drawing is for general information only. refer to jedec drawing ms-012, variation aa for proper dimensions, tolerances, datums, etc. 8s1, 8-lead (0.150? wide body), plastic gull wing small outline (jedec soic) swb
77 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 28.2 8s2 ? 8-l ead eiaj soic title drawing no. gpc rev. package drawing contact: contact@adestotech.com 8s2 stn f 8s2, 8-lead, 0.208? body, plastic small outline package (eiaj) 4/15/08 common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this drawing is for general information only; refer to eiaj drawing edr-7320 for additional information. 2. mismatch of the upper and lower dies and resin burrs aren't included. 3. determines the true geometric position. 4. values b,c apply to plated terminal. the standard thickness of the plating layer shall measure between 0.007 to .021 mm. a 1.70 2.16 a1 0.05 0.25 b 0.35 0.48 4 c 0.15 0.35 4 d 5.13 5.35 e1 5.18 5.40 2 e 7.70 8.26 l 0.51 0.85 q 0 8 e 1.27 bsc 3 q q 1 1 n n e e top view t o p v i e w c c e1 e 1 end view e n d v i e w a a b b l l a1 a 1 e e d d side view s i d e v i e w
78 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 28.3 8ma1 ? 8-pad udfn title drawing no. gpc rev. package drawing contact: contact@adestotech.com 8ma1 yfg d 8ma1, 8-pad (5 x 6 x 0.6 mm body), thermally enhanced plastic ultra thin dual flat no lead package (udfn) common dimensions (unit of measure = mm) symbol min nom max n o t e a 0.45 0.55 0.60 a1 0.00 0.02 0.05 b 0.35 0.40 0.48 c 0.152 ref d 4.90 5.00 5.10 d2 3.80 4.00 4.20 e 5.90 6.00 6.10 e2 3.20 3.40 3.60 e 1.27 l 0.50 0.60 0.75 y 0.00 ? 0.08 k 0.20 ? ? 4/15/08 pin 1 id top view e d a1 a side view y c bottom view e2 d2 l b e 1 2 3 4 8 7 6 5 pin #1 notch (0.20 r) 0.45 k pin #1 cham f e r (c 0.35) option a (option b)
79 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 28.4 9cc1 ? 9-ball ubga drawing no. rev. gpc title package drawing contact: contact@adestotech.com 9cc1 a cca 9cc1 , 9-ball, 6 x 6 x 0.6mm body, 1.0mm ball pitch (3x3 array), ultra-thin ball grid array package(ubga) 6/30/09 common dimensions (unit of measure = mm) symbol min nom max note notes: 1. dimension ?b? is measured at the maximum ball diameter, in a plane parallel to the seating plane. a ? 0.53 0.60 a1 0.12 ? - a2 0.38 ref d 5.90 6.00 6.10 d1 2.00 bsc e 5.90 6.00 6.10 e1 2.00 bsc b 0.35 0.40 0.45 note 1 e 1.00 bsc e d 9-?b b pin#1 id top view bottom view d 0.10 c a1 a d1 e1 a2 a1 ball corner e 2 side view see view "a" b a a a1 view "a" (rotated 90cw) section a-a e seating plane a c 3 1 b a c 2 3 1 c f 0.10 c a d 0.10 (4x) b j n 0.15 m cab j n 0.05 m c ?0.400.05 ?0.30 original/raw ball
80 at45dq161 [preliminary datasheet] 8790b?dflash?10/2013 29. revision history doc. rev. date comments 8790a 11/2012 initial document release. 8790b 10/2013 added extended temperature option and part numbers. updated document status from ?advanced? to ?preliminary?.
corporate office california | usa adesto headquarters 1250 borregas avenue sunnyvale, ca 94089 phone: (+1) 408.400.0578 email: contact@adestotech.com ? 2012 adesto technologies. all rights reserved. / rev.: 8790b?dflash?10/2013 disclaimer: adesto technologies corporation makes no warranty for the use of its products, other than those expressly contained in the company's standard warranty which is detailed in adesto's terms and conditions located on the company's web site. the company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. no lic enses to patents or other intellectual property of adesto are granted by the company in connection with the sale of adesto products, expressly or by implication. adesto's products are not authorized for u se as critical components in life support devices or systems. adesto ? , the adesto logo, cbram ? , and dataflash ? are registered trademarks or trademarks of adesto technologies. all other marks are the property of their respective owners.

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